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SN54HC273, SN74HC273
SCLS136E – DECEMBER 1982 – REVISED JULY 2016
SNx4HC273 Octal D-Type Flip-Flops With Clear
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The SNx4HC273 devices are positive-edge-triggered
D-type flip-flops with a direct active low clear (CLR)
input.
1
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up to 10 LSTTL Loads
Low Power Consumption, 80-µA Maximum ICC
Typical tpd = 12 ns
±4-mA Output Drive at 5 V
Low Input Current of 1-µA Maximum
Contain Eight Flip-Flops With Single-Rail Outputs
Direct Clear Input
Individual Data Input to Each Flip-Flop
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
2 Applications
•
•
•
Buffer or Storage Registers
Shift Registers
Pattern Generators
Information at the data (D) inputs meeting the setup
time requirements is transferred to the Q outputs on
the positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a particular voltage level
and is not related directly to the transition time of the
positive-going pulse. When CLK is at either the high
or low level, the D input has no effect at the output.
Device Information(1)
PART NUMBER
PACKAGE (PINS)
BODY SIZE (NOM)
SN54HC273J
CDIP (20)
24.20 mm × 6.92 mm
SN54HC273W
CFP (20)
13.09 mm × 6.92 mm
SN54HC273FK
LCCC (20)
8.89 mm × 8.89 mm
SN74HC273D
SOIC (20)
12.80 mm × 7.50 mm
SN74HC273DB
SSOP (20)
7.20 mm × 5.30 mm
SN74HC273NS
SO (20)
12.60 mm × 5.30 mm
SN74HC273N
PDIP (20)
24.33 mm × 6.35 mm
SN74HC273PW
TSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram, Each Flip-Flop (Positive Logic)
D
C
C
TG
TG
Q
C
C
C
C
TG
CLK(I)
TG
C
C
C
C
R
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC273, SN74HC273
SCLS136E – DECEMBER 1982 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
4
4
4
5
5
5
6
6
7
7
8
8
8
9
9
Absolute Maximum Ratings ......................................
ESD Ratings – SN74HC273 .....................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Electrical Characteristics – SN54HC273 ..................
Electrical Characteristics – SN74HC273 ..................
Timing Requirements ................................................
Timing Requirements – SN54HC273........................
Timing Requirements – SN74HC273......................
Switching Characteristics ........................................
Switching Characteristics – SN54HC273................
Switching Characteristics – SN74HC273................
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information ................ 10
8
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2003) to Revision E
Page
•
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
•
Removed Ordering Information table, see POA at the end of the data sheet........................................................................ 1
•
Added Military Disclaimer to Features.................................................................................................................................... 1
•
Changed RθJA for DB package from 70°C/W : to 90.3°C/W ................................................................................................... 5
•
Changed RθJA for DW package from 58°C/W : to 77.4°C/W .................................................................................................. 5
•
Changed RθJA for N package from 69°C/W : to 45.1°C/W...................................................................................................... 5
•
Changed RθJA for NS package from 60°C/W : to 72.6°C/W ................................................................................................... 5
•
Changed RθJA for PW package from 83°C/W : to 98.3°C/W .................................................................................................. 5
2
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SCLS136E – DECEMBER 1982 – REVISED JULY 2016
5 Pin Configuration and Functions
J, W, DB, DW N, NS, or PW Package
CDIP, CFP, SSOP, SOIC, SO, PDIP, or TSSOP
Top View
1D
1Q
CLR
VCC
8Q
3
2
1
20
19
FK Package
20-Pin LCCC
Top View
1Q
2
19
8Q
1D
3
18
8D
2D
4
17
7D
2D
4
18
8D
2Q
5
16
7Q
2Q
5
17
7D
3Q
6
15
6Q
3Q
6
16
7Q
3D
7
14
6D
3D
7
15
6Q
4D
8
13
5D
4D
8
14
6D
4Q
9
12
5Q
10
11
CLK
5D
5Q
GND
Not to scale
CLK
9
4Q
GND
13
VCC
12
20
11
1
10
CLR
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
CLR
I
Active low clear input
2
1Q
O
Output 1
3
1D
I
Input 1
4
2D
I
Input 2
5
2Q
O
Output 2
6
3Q
O
Output 3
7
3D
I
Input 3
8
4D
I
Input 4
9
4Q
O
Output 4
10
GND
—
Ground
11
CLK
I
Clock input
12
5Q
O
Output 5
13
5D
I
Input 5
14
6D
I
Input 6
15
6Q
O
Output 6
16
7Q
O
Output 7
17
7D
I
Input 7
18
8D
I
Input 8
19
8Q
O
Output 8
20
VCC
—
Power
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SCLS136E – DECEMBER 1982 – REVISED JULY 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
(2)
MIN
MAX
UNIT
–0.5
7
V
IIK
Input clamp current
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current (2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings – SN74HC273
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
NOM
MAX
2
5
6
VCC = 4.5 V
3.15
V
4.2
VCC = 2 V
Low-level input voltage
V
1.5
VCC = 6 V
VIL
UNIT
0.5
VCC = 4.5 V
1.35
VCC = 6 V
V
1.8
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2 V
∆t/∆v
TA
(1)
4
Input transition rise and fall time
Operating free-air temperature
1000
VCC = 4.5 V
500
VCC = 6 V
400
SN54HC273
–55
125
SN74HC273
–40
85
ns
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
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SCLS136E – DECEMBER 1982 – REVISED JULY 2016
6.4 Thermal Information
SN74HC273
THERMAL METRIC (1)
DB
(SSOP)
DW
(SOIC)
N
(PDIP)
NS
(SO)
PW
(TSSOP)
UNIT
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
RθJA
Junction-to-ambient thermal resistance
(2)
90.3
77.4
45.1
72.6
98.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.7
42.8
31.1
38.9
33.3
°C/W
RθJB
Junction-to-board thermal resistance
45.5
45.2
26
40.1
49.3
°C/W
ψJT
Junction-to-top characterization parameter
17.7
16.7
16.6
15.7
2
°C/W
ψJB
Junction-to-board characterization parameter
45.1
44.7
25.9
39.7
48.7
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.5 Electrical Characteristics
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VOH
VI = VIH or VIL
MIN
TYP
VCC = 2 V
1.9
1.998
VCC = 4.5 V
4.4
4.499
VCC = 6 V
5.9
5.999
3.98
4.3
IOH = –4 mA, VCC = 4.5 V
IOH = –5.2 mA, VCC = 6 V
UNIT
V
5.8
VCC = 2 V
0.002
0.1
VCC = 4.5 V
0.001
0.1
VCC = 6 V
0.001
0.1
IOL = 4 mA, VCC = 4.5 V
0.17
0.26
IOL = 5.2 mA, VCC = 6 V
0.15
0.26
±0.1
±100
nA
8
µA
3
10
pF
TYP
MAX
IOL = 20 µA
VOL
5.48
MAX
VI = VIH or VIL
II
VI = VCC or 0, VCC = 6 V
ICC
VI = VCC or 0, IO = 0, VCC = 6 V
Ci
VCC = 2 V to 6 V
V
6.6 Electrical Characteristics – SN54HC273
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VOH
VI = VIH or VIL
MIN
VCC = 2 V
1.9
VCC = 4.5 V
4.4
VCC = 6 V
5.9
IOH = –4 mA, VCC = 4.5 V
VOL
VI = VIH or VIL
5.2
VCC = 2 V
0.1
VCC = 4.5 V
0.1
VCC = 6 V
0.1
IOL = 4 mA, VCC = 4.5 V
IOL = 5.2 mA, VCC = V
II
VI = VCC or 0, VCC = 6 V
ICC
VI = VCC or 0, IO = 0, VCC = 6 V
Ci
VCC = 2 V to 6 V
V
3.7
IOH = –5.2 mA, VCC = 6 V
IOL = 20 µA
UNIT
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V
0.4
0.4
±1000
nA
160
µA
10
pF
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6.7 Electrical Characteristics – SN74HC273
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
IOH = –20 µA
VOH
VI = VIH or VIL
VCC = 2 V
1.9
VCC = 4.5 V
4.4
VCC = 6 V
IOH = –4 mA, VCC = 4.5 V
VOL
VI = VIH or VIL
MAX
5.9
UNIT
V
3.84
IOH = –5.2 mA, VCC = 6 V
IOL = 20 µA
TYP
5.34
VCC = 2 V
0.1
VCC = 4.5 V
0.1
VCC = 6 V
0.1
IOL = 4 mA, VCC = 4.5 V
0.33
IOL = 5.2 mA, VCC = 6 V
0.33
V
II
VI = VCC or 0, VCC = 6 V
±1000
nA
ICC
VI = VCC or 0, IO = 0, VCC = 6 V
80
µA
Ci
VCC = 2 V to 6 V
10
pF
6.8 Timing Requirements
TA = 25°C (unless otherwise noted)
MIN
VCC = 2 V
fclock
Clock frequency
CLR low
tw
Pulse duration
CLK high or low
Data
tsu
Setup time before CLK↑
CLR inactive
th
6
Hold time, data after CLK↑
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MAX
UNIT
5
VCC = 4.5 V
27
VCC = 6 V
32
VCC = 2 V
80
VCC = 4.5 V
16
VCC = 6 V
14
VCC = 2 V
80
VCC = 4.5 V
16
VCC = 6 V
14
VCC = 2 V
100
VCC = 4.5 V
MHz
ns
20
VCC = 6 V
17
VCC = 2 V
100
VCC = 4.5 V
20
VCC = 6 V
17
VCC = 2 V
0
VCC = 4.5 V
0
VCC = 6 V
0
ns
ns
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6.9 Timing Requirements – SN54HC273
over recommended operating free-air temperature range (unless otherwise noted)
MIN
VCC = 2 V
fclock
Clock frequency
18
VCC = 6 V
21
tw
Pulse duration
CLK high or low
Data
tsu
Setup time before CLK↑
CLR inactive
th
Hold time, data after CLK↑
VCC = 4.5 V
24
20
VCC = 2 V
120
ns
24
VCC = 6 V
20
VCC = 2 V
150
VCC = 4.5 V
MHz
120
VCC = 6 V
VCC = 4.5 V
UNIT
4
VCC = 4.5 V
VCC = 2 V
CLR low
MAX
30
VCC = 6 V
25
VCC = 2 V
150
VCC = 4.5 V
30
VCC = 6 V
25
VCC = 2 V
0
VCC = 4.5 V
0
VCC = 6 V
0
ns
ns
6.10 Timing Requirements – SN74HC273
over recommended operating free-air temperature range (unless otherwise noted)
MIN
VCC = 2 V
fclock
Clock frequency
21
VCC = 6 V
25
tw
Pulse duration
CLK high or low
Data
tsu
Setup time before CLK↑
CLR inactive
th
Hold time, data after CLK↑
VCC = 4.5 V
20
17
VCC = 2 V
100
17
VCC = 2 V
125
25
VCC = 6 V
21
VCC = 2 V
125
VCC = 4.5 V
25
VCC = 6 V
21
VCC = 2 V
0
VCC = 4.5 V
0
VCC = 6 V
0
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ns
20
VCC = 6 V
VCC = 4.5 V
MHz
100
VCC = 6 V
VCC = 4.5 V
UNIT
4
VCC = 4.5 V
VCC = 2 V
CLR low
MAX
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ns
ns
7
SN54HC273, SN74HC273
SCLS136E – DECEMBER 1982 – REVISED JULY 2016
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6.11 Switching Characteristics
TA = 25°C and CL = 50 pF (unless otherwise noted; see Figure 2)
PARAMETER
TEST CONDITIONS
VCC = 2 V
fmax
tPHL
From CLR (input) to any (output)
tpd
From CLK (input) to any (output)
tt
To any (output)
MIN
TYP
5
11
VCC = 4.5 V
27
50
VCC = 6 V
32
60
MAX
UNIT
MHz
VCC = 2 V
55
160
VCC = 4.5 V
15
32
VCC = 6 V
12
27
VCC = 2 V
56
160
VCC = 4.5 V
15
32
VCC = 6 V
13
27
VCC = 2 V
38
75
VCC = 4.5 V
8
15
VCC = 6 V
6
13
ns
ns
ns
6.12 Switching Characteristics – SN54HC273
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted; see Figure 2)
PARAMETER
TEST CONDITIONS
MIN
VCC = 2 V
fmax
VCC = 4.5 V
18
VCC = 6 V
21
VCC = 2 V
tPHL
From CLR (input) to any (output)
tpd
From CLK (input) to any (output)
tt
To any (output)
MAX
UNIT
4
MHz
240
VCC = 4.5 V
48
VCC = 6 V
41
VCC = 2 V
240
VCC = 4.5 V
48
VCC = 6 V
41
VCC = 2 V
110
VCC = 4.5 V
22
VCC = 6 V
19
ns
ns
ns
6.13 Switching Characteristics – SN74HC273
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted; see Figure 2)
PARAMETER
TEST CONDITIONS
MIN
VCC = 2 V
fmax
VCC = 4.5 V
21
VCC = 6 V
25
VCC = 2 V
tPHL
tpd
tt
8
From CLR (input) to any (output)
From CLK (input) to any (output)
To any (output)
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MAX
UNIT
4
MHz
200
VCC = 4.5 V
40
VCC = 6 V
34
VCC = 2 V
200
VCC = 4.5 V
40
VCC = 6 V
34
VCC = 2 V
95
VCC = 4.5 V
19
VCC = 6 V
16
ns
ns
ns
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6.14 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per flip-flop
TYP
No load
UNIT
35
pF
6.15 Typical Characteristics
200
160
120
tpd(max)(ns)
Ta =25o C
CL = 50pF
CLK to Q/Q
80
30
20
2
0
4
5
6
Vcc
Figure 1. Max tpd vs VCC
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7 Parameter Measurement Information
From Output
Under Test
VCC
High-Level
Pulse
Test
Point
50%
50%
0V
tw
CL = 50 pF
(see Note A)
VCC
Low-Level
Pulse
50%
50%
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
VCC
50%
50%
0V
tPLH
Reference
Input
VCC
50%
In-Phase
Output
0V
tsu
Data
Input 50%
10%
90%
tr
tPHL
VCC
50%
10% 0 V
Out-of-Phase
Output
90%
90%
VOH
50%
10%
VOL
tf
tPLH
50%
10%
tf
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
90%
tr
th
90%
50%
10%
tPHL
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
The SNx4HC273 contains eight flip-flops with single-rail outputs with individual data input to each flip-flop. The
outputs can drive up to 10 LSTTL loads. The device has direct active low clear input.
8.2 Functional Block Diagram
2D
1D
3
3D
4
4D
7
5D
8
6D
13
7D
14
8D
17
18
11
CLK
1D
1D
C1
C1
R
CLR
1D
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
C1
R
R
1
2
5
1Q
6
2Q
9
3Q
4Q
12
15
5Q
6Q
16
7Q
19
8Q
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8.3 Feature Description
The SNx4HC273 has low power consumption with a maximum
CC
of 80 µA.
The typical tpd for the SNx4HC273 is 12 ns and the output drive is ±4 mA at 5 V.
The SNx4HC273 also has very low input current, with the maximum set at 1 µA.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SNx4HC273.
Table 1. Function Table (Each Flip-Flop)
INPUTS
D
OUTPUT
Q
CLR
CLK
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Q0
Copyright © 1982–2016, Texas Instruments Incorporated
Product Folder Links: SN54HC273 SN74HC273
Submit Documentation Feedback
11
SN54HC273, SN74HC273
SCLS136E – DECEMBER 1982 – REVISED JULY 2016
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SNx4HC273 is octal D Flip flop with active low clear input. It has low input current and low power
consumption. The D flip-flop can be used as a Toggle flip flop using an XOR gate at the input. The output toggles
from the previous state whenever the T input is high.
9.2 Typical Application
T
Q
D
CLR
CLK
Copyright © 2016, Texas Instruments Incorporated
9.2.1 Design Requirements
This SNx4Hc273 device uses CMOS technology and has balanced output drive.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– Rise time and fall time specifications: see (Δt/ΔV) in Recommended Operating Conditions.
– Specified high and low levels: see (VIH and VIL) in Recommended Operating Conditions.
– Inputs are not overvoltage tolerant and must not be above any valid VCC as per Recommended Operating
Conditions.
2. Absolute maximum output conditions:
– Continuos output currents must not exceed (IO max) per output and must not exceed total current
(continuous current through VCC or GND) for the part. These limits are located in the Absolute Maximum
Ratings.
– Outputs must not be pulled above VCC.
12
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Copyright © 1982–2016, Texas Instruments Incorporated
Product Folder Links: SN54HC273 SN74HC273
SN54HC273, SN74HC273
www.ti.com
SCLS136E – DECEMBER 1982 – REVISED JULY 2016
Typical Application (continued)
9.2.3 Application Curve
80
70
60
tt(max)(ns)
Ta =25o C
CL = 50pF
Q/Q
50
20
10
2
0
4
5
6
Vcc
Figure 3. Max Transition Time vs VCC
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
TI recommends a 0.1-µF capacitor. If there are multiple VCC pins, TI recommends a 0.01-µF or 0.022-µF
capacitor for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise.
0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to
the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs must not ever float. In many cases, functions or parts of functions of
digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3
of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at
the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances:
• All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from
floating.
• The logic level that must be applied to any particular unused input depends on the function of the device.
• Generally they are tied to GND or VCC whichever make more sense or is more convenient.
11.2 Layout Example
VCC
Input
Unused Input
Output
Unused Input
Output
Input
Figure 4. SNx4HC273 Layout
Copyright © 1982–2016, Texas Instruments Incorporated
Product Folder Links: SN54HC273 SN74HC273
Submit Documentation Feedback
13
SN54HC273, SN74HC273
SCLS136E – DECEMBER 1982 – REVISED JULY 2016
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54HC273
Click here
Click here
Click here
Click here
Click here
SN74HC273
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
14
Submit Documentation Feedback
Copyright © 1982–2016, Texas Instruments Incorporated
Product Folder Links: SN54HC273 SN74HC273
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-8409901VRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
5962-8409901VR
A
SNV54HC273J
5962-8409901VSA
ACTIVE
CFP
W
20
25
TBD
A42
N / A for Pkg Type
5962-8409901VS
A
SNV54HC273W
84099012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84099012A
SNJ54HC
273FK
8409901RA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409901RA
SNJ54HC273J
8409901SA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409901SA
SNJ54HC273W
JM38510/65601BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65601BRA
JM38510/65601BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65601BSA
M38510/65601BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65601BRA
M38510/65601BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65601BSA
SN54HC273J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54HC273J
SN74HC273DBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
-40 to 85
SN74HC273DBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
SN74HC273DBRG4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
SN74HC273DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
SN74HC273DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
SN74HC273DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
25-Oct-2016
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74HC273DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
HC273
SN74HC273DWRE4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
SN74HC273DWRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
SN74HC273N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC273N
SN74HC273N3
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
-40 to 85
SN74HC273NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC273N
SN74HC273NSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
SN74HC273NSRG4
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
SN74HC273PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
SN74HC273PWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
SN74HC273PWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
-40 to 85
SN74HC273PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
SN74HC273PWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
SN74HC273PWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC273
SNJ54HC273FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84099012A
SNJ54HC
273FK
SNJ54HC273J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409901RA
SNJ54HC273J
SNJ54HC273W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409901SA
SNJ54HC273W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC273, SN54HC273-SP, SN74HC273 :
• Catalog: SN74HC273, SN54HC273
• Automotive: SN74HC273-Q1, SN74HC273-Q1
• Military: SN54HC273
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
• Space: SN54HC273-SP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74HC273DBR
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
SN74HC273DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74HC273DWRG4
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74HC273NSR
SO
NS
20
2000
330.0
24.4
9.0
13.0
2.4
12.0
24.0
Q1
SN74HC273PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74HC273PWT
TSSOP
PW
20
250
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HC273DBR
SSOP
DB
20
2000
367.0
367.0
38.0
SN74HC273DWR
SOIC
DW
20
2000
600.0
144.0
84.0
SN74HC273DWRG4
SOIC
DW
20
2000
367.0
367.0
45.0
SN74HC273NSR
SO
NS
20
2000
367.0
367.0
45.0
SN74HC273PWR
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74HC273PWT
TSSOP
PW
20
250
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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