SN54HC377, SN74HC377
SCLS307D – JANUARY 1996 – REVISED MAY 2022
SNx4HC377 Octal D-Type Flip-Flops With Clock Enable
1 Features
3 Description
•
•
•
•
•
•
•
•
These devices are positive-edge-triggered octal Dtype flip-flops with an enable input. The ’HC377
devices are similar to the ’HC273 devices, but feature
a latched clock-enable (CLKEN) input instead of a
common clear.
Wide operating voltage range of 2 V to 6 V
Outputs can drive up to 10 LSTTL loads
Low power consumption, 80-µA max ICC
Typical tpd = 12 ns
±4-mA output drive at 5 V
Low input current of 1 µA max
Eight flip-flops with single-rail outputs
Clock enable latched to avoid false clocking
2 Applications
•
•
•
Buffer/storage registers
Shift registers
Pattern generators
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HC377DW
SOIC (20)
12.80 mm × 7.50 mm
SN74HC377N
PDIP (20)
25.40 mm × 6.35 mm
SN74HC377NS
SO (20)
15.00 mm × 5.30 mm
SN54HC377J
CDIP (20)
26.92 mm × 6.92 mm
SNJ54HC377FK
LCCC (20)
8.89 mm × 8.45 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC377, SN74HC377
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SCLS307D – JANUARY 1996 – REVISED MAY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
(1)
6.2 Recommended Operating Conditions ..................... 4
6.3 Thermal Information....................................................4
6.4 Electrical Characteristics.............................................5
6.5 Timing Requirements.................................................. 5
6.6 Switching Characteristics ...........................................6
6.7 Operating Characteristics........................................... 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Device Functional Modes............................................9
9 Power Supply Recommendations................................10
10 Layout...........................................................................10
10.1 Layout Guidelines................................................... 10
11 Device and Documentation Support.......................... 11
11.1 Documentation Support...........................................11
11.2 Receiving Notification of Documentation Updates.. 11
11.3 Support Resources..................................................11
11.4 Trademarks............................................................. 11
11.5 Electrostatic Discharge Caution.............................. 11
11.6 Glossary.................................................................. 11
12 Mechanical, Packaging, and Orderable
Information.................................................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (January 2022) to Revision D (May 2022)
Page
• Junction-to-ambient thermal resistance values increased. DW was 58 is now 109.1, N was 69 is now 84.6,
NS was 60 is now 113.4......................................................................................................................................4
Changes from Revision B (January 2003) to Revision C (January 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCLS307D – JANUARY 1996 – REVISED MAY 2022
5 Pin Configuration and Functions
J, DW, N, or NS package
20-Pin CDIP, SOIC, PDIP, SO
Top View
FK package
20-Pin LCCC
Top View
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SCLS307D – JANUARY 1996 – REVISED MAY 2022
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage range
(2)
IIK
Input clamp current
IOK
Output clamp current
IO
Continuous output current
(2)
MIN
MAX
-0.5
7
Junction temperature
Tstg
Storage temperature
(1)
(2)
V
(VI < 0 or VI > VCC)
±20
mA
(VO < 0 or VO > VCC)
±20
mA
(VO = 0 to VCC)
±25
mA
±50
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
UNIT
-65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(1)
6.2 Recommended Operating Conditions
SN54HC377
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
VCC = 4.5 V
VCC = 6 V
NOM
MAX
2
5
6
Low-level input voltage
VI
Input voltage
VO
Output voltage
TA
(1)
MAX
2
5
6
3.15
3.15
4.2
4.2
VCC = 4.5 V
0
0.5
0.5
1.35
0
VCC
0
V
VCC
V
VCC = 4.5 V
500
500
VCC = 6 V
400
400
125
V
VCC
1000
– 55
V
1.8
VCC
1000
Operating free-air temperature
UNIT
V
1.35
1.8
0
VCC = 2 V
Input transition rise/fall time
NOM
1.5
VCC = 6 V
tt
MIN
1.5
VCC = 2 V
VIL
SN74HC377
MIN
– 40
85
ns
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating SMOS Inputs, literature number SCBA004.
6.3 Thermal Information
THERMAL METRIC
4
(1)
DW (SOIC)
N (PDIP)
NS (SO)
20 PINS
20 PINS
20 PINS
UNIT
109.1
84.6
113.4
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
76
72.5
78.6
°C/W
RθJB
Junction-to-board thermal resistance
77.6
65.3
78.4
°C/W
ψJT
Junction-to-top characterization
parameter
51.5
55.3
47.1
°C/W
ψJB
Junction-to-top characterization
parameter
77.1
65.2
78.1
°C/W
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6.3 Thermal Information (continued)
DW (SOIC)
N (PDIP)
NS (SO)
20 PINS
20 PINS
20 PINS
UNIT
N/A
N/A
N/A
°C/W
THERMAL METRIC
RθJC(bot)
(1)
Junction-to-case (bottom) thermal
resistance
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
6.4 Electrical Characteristics
PARAMETER
TEST CONDITIONS(1)
IOH = –20 μA
VOH
IOH = –4 mA
IOH = – 5.2 mA
VCC (V)
TA = 25°C
SN74HC377
MAX
MIN
SN74HC377
MIN
TYP
MAX
MIN
2
1.9
1.998
1.9
1.9
4.5
4.4
4.499
4.4
4.4
6
5.9
5.999
5.9
5.9
4.5
3.98
4.3
3.7
3.84
6
5.48
5.8
5.2
5.34
V
2
0.002
0.1
0.1
0.1
IOL = 20 μA
4.5
0.001
0.1
0.1
0.1
6
0.001
0.1
0.1
0.1
IOL = 4 mA
4.5
0.17
0.26
0.4
0.33
VOL
UNIT
MAX
V
IOL = 5.2 mA
6
0.15
0.26
0.4
0.33
II
VI = VCC or 0
6
±0.1
±100
±1000
±1000
nA
ICC
VI = VCC or 0. IO = 0
8
160
80
μA
3
10
10
10
pF
6
Ci
(1)
2 to 6
VI = VIH or VIL, unless otherwise noted.
6.5 Timing Requirements
VCC
fclock
Clock frequency
TA = 25°C
MIN
Pulse duration, CLK high or low
D
tsu
Setup time, data before
CLK↑
CLKEN high or low
th
Hold time, data after LE↑
CLKEN inactive or active,
data
MIN
SN74HC377
MAX
2
5
3
4.5
25
16
6
tW
SN54HC377
MAX
29
MIN
MAX
UNIT
4
20 MHz
19
23
2
100
150
125
4.5
20
30
25
6
17
25
21
2
100
150
125
4.5
20
30
25
6
17
25
21
2
100
150
125
4.5
20
30
25
6
17
25
21
2
5
5
5
4.5
5
5
5
6
5
5
5
ns
ns
ns
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SCLS307D – JANUARY 1996 – REVISED MAY 2022
6.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) See Parameter Measurement
Information
PARAM
ETER
FROM (INPUT)
TO (OUTPUT)
fmax
tpd
CLK
Any
tt
Any
VCC (V)
TA = 25°C
MIN
TYP
SN54HC377
MAX
MIN
SN74HC377
MAX
MIN
2
5
11
3
4
4.5
25
54
16
20
6
29
64
19
MAX
UNIT
MHz
23
2
56
160
240
200
4.5
15
32
48
40
6
12
27
41
34
2
38
75
110
95
4.5
8
15
22
19
6
6
13
19
16
ns
ns
6.7 Operating Characteristics
TA = 25°C
Cpd
6
Power dissipation capacitance per flip-flop
Test Conditions
TYP
UNIT
No load
30
pF
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 7-1. Load Circuit for Push-Pull Outputs
tw
VCC
Clock
Input
VCC
Input
50%
50%
50%
0V
0V
Figure 7-2. Voltage Waveforms, Standard CMOS
Inputs Pulse Duration
th
tsu
VCC
Data
Input
50%
50%
0V
Figure 7-3. Voltage Waveforms, Standard CMOS
Inputs Setup and Hold Times
VCC
Input
50%
90%
Input
50%
tPLH
tPHL
10%
10%
0V
(1)
tr(1)
(1)
VOH
Output
50%
VOL
tPHL
tPLH
50%
90%
VOH
90%
10%
50%
10%
tr(1)
(1)
VOH
Output
0V
tf(1)
Output
50%
(1)
VCC
90%
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 7-5. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Inputs
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-4. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
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8 Detailed Description
8.1 Overview
These devices are positive-edge-triggered octal D-type flip-flops with an enable input. The ’HC377 devices are
similar to the ’HC273 devices, but feature a latched clock-enable (CLKEN) input instead of a common clear.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse, if CLKEN is low. Clock triggering occurs at a particular voltage level
and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low
level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions
at CLKEN.
8.2 Functional Block Diagram
8
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8.3 Device Functional Modes
Function Table
(Each Flip-Flop)
INPUTS
CLKEN
CLK
D
OUTPUT
Q
H
X
X
Q0
L
↑
H
H
L
↑
L
L
X
L
X
Q0
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SCLS307D – JANUARY 1996 – REVISED MAY 2022
9 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
10 Layout
10.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
10
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Documentation Support
11.1.1 Related Documentation
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-87807012A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
596287807012A
SNJ54HC
377FK
5962-8780701RA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8780701RA
SNJ54HC377J
Samples
SN54HC377J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SN54HC377J
Samples
SN74HC377DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC377
Samples
SN74HC377DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC377
Samples
SN74HC377N
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC377N
Samples
SN74HC377NE4
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC377N
Samples
SN74HC377NSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC377
Samples
SNJ54HC377FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
596287807012A
SNJ54HC
377FK
SNJ54HC377J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8780701RA
SNJ54HC377J
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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