SN74HC4060N


  
 

  
 
 
SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 14 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Allow Design of Either RC- or Crystal-Oscillator Circuits 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QJ QH QI CLR CLKI CLKO CLKO QN QF NC QE QG 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QH QI NC CLR CLKI QD GND NC CLKO CLKO QL QM QN QF QE QG QD GND SN54HC4060 . . . FK PACKAGE (TOP VIEW) QM QL SN54HC4060 . . . J OR W PACKAGE SN74HC4060 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) NC VCC QJ D D D D NC − No internal connection description/ordering information The ’HC4060 devices consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC- or crystal-oscillator circuits. A high-to-low transition on the clock (CLKI) input increments the counter. A high level at the clear (CLR) input disables the oscillator (CLKO goes high and CLKO goes low) and resets the counter to zero (all Q outputs low). ORDERING INFORMATION PACKAGE† TA PDIP − N SN74HC4060N Tube of 40 SN74HC4060D Reel of 2500 SN74HC4060DR Reel of 250 SN74HC4060DT SOP − NS Reel of 2000 SN74HC4060NSR HC4060 SSOP − DB Reel of 2000 SN74HC4060DBR HC4060 Tube of 90 SN74HC4060PW Reel of 2000 SN74HC4060PWR TSSOP − PW −55°C −55 C to 125 125°C C TOP-SIDE MARKING Tube of 25 SOIC − D −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER SN74HC4060N HC4060 HC4060 Reel of 250 SN74HC4060PWT CDIP − J Tube of 25 SNJ54HC4060J SNJ54HC4060J CFP − W Tube of 150 SNJ54HC4060W SNJ54HC4060W LCCC − FK Tube of 55 SNJ54HC4060FK SNJ54HC4060FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated     !" # $%&" !#  '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&#  &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+  '*%$"# $')!" " 12343 !)) '!!&"&# !& "&#"&* %)&## ",&.#& "&*+  !)) ",& '*%$"# '*%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 

  
 

  
 
 
SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 FUNCTION TABLE (each buffer) INPUTS FUNCTION CLK CLR ↑ L No change ↓ L Advance to next stage X H All outputs L logic diagram (positive logic) R R T CLR R T R T 4 6 QF QG R T 14 R T 13 QH T R T 15 QI QJ R T T 1 2 3 QL QM QN 12 R R T 9 CLKI R 11 10 R T R T R T T CLKO CLKO Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. 7 5 QD QE absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

  
 

  
 
 
SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 3) SN54HC4060 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO ∆t/∆v MIN NOM MAX 2 5 6 Input voltage MAX 2 5 6 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition rise/fall time NOM 1.5 0 Output voltage MIN 1.5 VCC = 4.5 V VCC = 6 V Low-level input voltage SN74HC4060 0 VCC VCC 0 1000 1000 500 500 400 400 V V V ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54HC4060 MIN MAX SN74HC4060 MIN 2V 1.9 1.998 1.9 1.9 4.4 4.499 4.4 4.4 MAX UNIT VI = VIH or VIL, IOH = −20 µA 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 Q outputs VI = VIH or VIL IOH = −4 mA IOH = −5.2 mA 6V 5.48 5.8 5.2 5.34 2V 0.002 0.1 0.1 0.1 All outputs VI = VIH or VIL, IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 8 160 80 µA 10 10 10 pF VOH VOL Q outputs Ci TA = 25°C MIN TYP MAX 4.5 V All outputs II ICC VCC VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, IOL = 4 mA IOL = 5.2 mA IO = 0 6V 2 V to 6 V POST OFFICE BOX 655303 3 • DALLAS, TEXAS 75265 V V 3 

  
 

  
 
 
SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency CLKI high or low tw Pulse duration CLR high tsu Setup time, CLR inactive before CLKI↓ TA = 25°C MIN MAX SN54HC4060 MIN MAX SN74HC4060 MIN MAX 2V 5.5 3.7 4.3 4.5 V 28 19 22 6V 33 22 25 2V 90 135 115 4.5 V 18 27 23 6V 15 23 20 2V 90 135 115 4.5 V 18 27 23 6V 15 23 20 2V 160 240 200 4.5 V 32 48 40 6V 27 41 34 UNIT MHz ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd CLKI tPHL CLR tt QD Any Q Any VCC TA = 25°C MIN TYP MAX SN54HC4060 MIN MAX SN74HC4060 MIN 2V 5.5 10 3.7 4.3 4.5 V 28 45 19 22 6V 33 53 22 25 MAX UNIT MHz 2V 240 490 735 615 4.5 V 58 98 147 123 6V 42 83 125 105 2V 66 140 210 175 4.5 V 18 28 42 35 6V 14 24 36 30 2V 28 75 110 95 4.5 V 8 15 22 19 6V 6 30 19 16 ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 88 UNIT pF 

  
 

  
 
 
SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Reference Input 0V CL = 50 pF (see Note A) tsu Data Input LOAD CIRCUIT Input 50% 0V tPLH In-Phase Output 90% 50% 10% 90% tPHL 90% VCC 50% 10% 0 V 90% tr tf VOLTAGE WAVEFORMS SETUP AND INPUT RISE AND FALL TIMES tPHL 90% tr Out-of-Phase Output 50% 10% VCC 50% VCC 50% VOH 50% 10% VOL tf tf 50% 10% 50% 50% 0V tPLH 50% 10% VCC High-Level Pulse VOH 90% VOL tr tw VCC Low-Level Pulse VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% 50% 0V VOLTAGE WAVEFORMS PULSE DURATIONS NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 

  
 

  
 
 
SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 CONNECTING AN RC-OSCILLATOR CIRCUIT TO THE ’HC4060 DEVICES The ’HC4060 devices consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC- or crystal-oscillator circuits. When an RC-oscillator circuit is implemented, two resistors and a capacitor are required. The components are attached to the terminals as shown: 1 2 16 15 3 4 14 13 5 6 12 11 7 10 8 9 R2 R1 C To determine the values of capacitance and resistance necessary to obtain a specific oscillator frequency (f), use this formula: f+ 1 R2 2(R1)(C)ǒ0.405 ) 0.693Ǔ R1)R2 If R2 > > R1 (i.e., R2 = 10R1), the above formula simplifies to: f + 0.455 RC 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN54HC4060FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN54HC 4060FK Samples SN74HC4060D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 Samples SN74HC4060DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 Samples SN74HC4060DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 Samples SN74HC4060DT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 Samples SN74HC4060N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC4060N Samples SN74HC4060NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 Samples SN74HC4060NSRE4 ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 Samples SN74HC4060PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 Samples SN74HC4060PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC4060 Samples SN74HC4060PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 Samples SN74HC4060PWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of