SN54HC573A, SN74HC573A
SCLS147G – DECEMBER 1982 – REVISED APRIL 2022
SNx4HC573A Octal Transparent D-Type Latches With 3-State Outputs
1 Features
3 Description
•
•
The SNx4HC573A devices are octal transparent
D-type latches that feature 3-state outputs designed
specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
•
•
•
•
•
Wide Operating Voltage Range from 2 V to 6 V
High-Current 3-State Outputs Drive Bus Lines
Directly up to 15 LSTTL Loads
Low Power Consumption: 80-µA Maximum ICC
Typical tpd = 21 ns
±6-mA Output Drive at 5 V
Low Input Current: 1 µA (Maximum)
Bus-Structured Pinout
While the latch-enable (LE) input is high, the
Q outputs respond to the data (D) inputs. When LE is
low, the outputs are latched to retain the data that was
set up.
2 Applications
•
•
•
Buffer Registers
Bidirectional Bus Drivers
Working Registers
Device Information(1)
PART NUMBER
LE
26.92 mm × 6.92 mm
SN54HC573AW
CFP (20)
13.72 mm × 6.92 mm
SN54HC573AFK
LCCC (20)
8.89 mm × 8.89 mm
SN74HC573AN
PDIP (20)
25.40 mm × 6.35 mm
SN74HC573ADW
SOIC (20)
12.80 mm × 7.50 mm
SN74HC573ADB
SSOP (20)
7.20 mm × 5.30 mm
SN74HC573APW
TSSOP (20)
5.00 mm × 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
1
11
C1
1D
BODY SIZE (NOM)
CDIP (20)
(1)
OE
PACKAGE
SN54HC573AJ
2
19
1Q
1D
To Seven Other Channels
Copyright © 2016, Texas Instruments Incorporated
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SCLS147G – DECEMBER 1982 – REVISED APRIL 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 6
6.7 Switching Characteristics............................................7
6.8 Typical Characteristics................................................ 9
7 Parameter Measurement Information.......................... 10
8 Detailed Description...................................................... 11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................11
9 Application and Implementation.................................. 12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
10 Power Supply Recommendations..............................13
11 Layout........................................................................... 14
11.1 Layout Guidelines................................................... 14
11.2 Layout Example...................................................... 14
12 Device and Documentation Support..........................15
12.1 Documentation Support.......................................... 15
12.2 Related Links.......................................................... 15
12.3 Receiving Notification of Documentation Updates..15
12.4 Support Resources................................................. 15
12.5 Trademarks............................................................. 15
12.6 Electrostatic Discharge Caution..............................15
12.7 Glossary..................................................................15
13 Mechanical, Packaging, and Orderable
Information.................................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2003) to Revision F (October 2016)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Deleted Ordering Information table; see POA at the end of the data sheet....................................................... 1
• Changed Package thermal impedance, RθJA, values from 70 to 92.5 (DB), from 58 to 78.3 (DW), from 69 to
49.1 (N), and from 83 to 101.1 (PW).................................................................................................................. 5
Changes from Revision F (October 2016) to Revision G (April 2022)
Page
• Updated ESD ratings table to modern TI standards........................................................................................... 4
• Changed Package thermal impedance, RθJA, values from 92.5 to 122.7 (DB), from 78.3 to 109.1 (DW), from
49.1 to 84.6 (N), and from 101.1 to 131.8 (PW)................................................................................................. 5
2
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SCLS147G – DECEMBER 1982 – REVISED APRIL 2022
5 Pin Configuration and Functions
DB, DW, J, N, PW, or W Packages
20-Pin SSOP, SOIC, CDIP, PDIP, TSSOP, or CFP
Top View
FK Package
20-Pin LCCC
Top View
Pin Functions
PIN
NO.
(1)
NAME
I/O
DESCRIPTION
1
OE
I
Output enable
2
1D
I
1D input
3
2D
I
2D input
4
3D
I
3D input
5
4D
I
4D input
6
5D
I
5D input
7
6D
I
6D input
8
7D
I
7D input
9
8D
I
8D input
10
GND
—
Ground
11
LE
I
Latch enable input
12
8Q
O
8Q output
13
7Q
O
7Q output
14
6Q
O
6Q output
15
5Q
O
5Q output
16
4Q
O
4Q output
17
3Q
O
3Q output
18
2Q
O
2Q output
19
1Q
O
1Q output
20
VCC
—
Power pin
(1)
Signal Types: I = Input, O = Output, I/O = Input or Output.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage
current(2)
MIN
MAX
UNIT
–0.5
7
V
IIK
Input clamp
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
±70
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±3500
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
MIN
NOM
MAX
2
5
6
Low-level input voltage
V
4.2
0.5
VCC = 4.5 V
1.35
VCC = 6 V
V
1.8
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2 V
tt
TA
(1)
4
V
1.5
3.15
VCC = 2 V
VIL
UNIT
Input transition (rise and fall) time
Operating free-air temperature
1000
VCC = 4.5 V
500
VCC = 6 V
400
SN54HC573A
–55
125
SN74HC573A
–40
85
ns
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the Implications of Slow or
Floating CMOS Inputs application report (SCBA004).
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6.4 Thermal Information
SN74HC573A
THERMAL METRIC
DW (SOIC)
DB (SSOP)
N (PDIP)
PW (TSSOP)
20 PINS
20 PINS
20 PINS
20 PINS
UNIT
109.1
122.7
84.6
131.8
°C/W
76
81.6
72.5
72.2
°C/W
RθJA
Junction-to-ambient thermal
(1)
resistance
RθJC (top)
Junction-to-case (top) thermal
resistance
RθJB
Junction-to-board thermal
resistance
77.6
77.5
65.3
82.8
°C/W
ΨJT
Junction-to-top characterization
parameter
51.5
46.1
55.3
21.5
°C/W
ΨJB
Junction-to-board characterization
parameter
77.1
77.1
65.2
82.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
N/A
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VOH
VI = VIH or VIL
IOH = –6 mA, VCC = 4.5 V
IOH = –7.8 mA, VCC = 6 V
IOL = 20 µA
VOL
IOL = 6 mA, VCC = 4.5 V
VI = VIH or VIL
MIN
TYP
VCC = 2 V
1.9
1.998
VCC = 4.5 V
4.4
4.499
VCC = 6 V
5.9
5.999
TA = 25°C
3.98
4.3
SN54HC573A
3.7
SN74HC573A
3.84
TA = 25°C
5.48
SN54HC573A
5.2
SN74HC573A
5.34
5.8
VCC = 2 V
0.002
0.1
VCC = 4.5 V
0.001
0.1
VCC = 6 V
0.001
0.1
TA = 25°C
0.17
0.26
SN54HC573A
TA = 25°C
II
VI = VCC or 0, VCC = 6 V
0.4
IOZ
VO = VCC or 0, VCC = 6 V
0.4
0.33
±0.1
SNx4HC573A
VI = VCC or 0, IO = 0, VCC = 6 V
Ci
VCC = 2 V to 6 V
±100
±1000
±0.01
nA
±0.5
SN54HC573A
±10
SN74HC573A
±5
TA = 25°C
ICC
0.26
SN74HC573A
TA = 25°C
V
0.33
0.15
SN54HC573A
TA = 25°C
UNIT
V
SN74HC573A
IOL = 7.8 mA, VCC = 6 V
MAX
µA
8
SN54HC573A
160
SN74HC573A
µA
80
3
10
pF
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
Cpd
Power dissipation
capacitance
per latch
TEST CONDITIONS
MIN
TA = 25°C, no load
TYP
MAX
50
UNIT
pF
6.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
MIN
TA = 25°C
VCC = 2 V
tw
Pulse duration, LE high
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
tsu
Setup time, data before LE↓
VCC = 4.5 V
SN54HC573A
120
SN74HC573A
100
TA = 25°C
16
SN54HC573A
24
SN74HC573A
20
TA = 25°C
14
SN54HC573A
20
SN74HC573A
17
TA = 25°C
50
SN54HC573A
75
SN74HC573A
63
TA = 25°C
10
SN54HC573A
15
SN74HC573A
13
TA = 25°C
VCC = 6 V
VCC = 2 V
th
6
Hold time, data after LE↓
SN54HC573A
MAX
UNIT
ns
ns
9
13
SN74HC573A
11
TA = 25°C
20
SNx4HC573A
24
VCC = 4.5 V
5
VCC = 6 V
5
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NOM
80
ns
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6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted; see Figure 7-1)
PARAMETER
TEST CONDITIONS
MIN
TA = 25°C
VCC = 2 V
TYP
MAX
77
175
SN54HC573A
265
SN74HC573A
CL = 50 pF, from D (input)
to Q (output)
TA = 25°C
VCC = 4.5 V
220
26
53
SN74HC573A
44
23
SN54HC573A
TA = 25°C
VCC = 2 V
38
87
SN54HC573A
CL = 50 pF, from LE (input)
to any Q (output)
VCC = 4.5 V
53
44
23
SN54HC573A
ten
CL = 50 pF, from OE (input)
to any Q (output)
38
68
225
SN74HC573A
190
24
SN54HC573A
TA = 25°C
38
32
47
SN54HC573A
tdis
VCC = 4.5 V
190
23
30
SN54HC573A
45
SN74HC573A
38
TA = 25°C
VCC = 6 V
150
225
SN74HC573A
CL = 50 pF, from OE (input)
to any Q (output)
26
SN74HC573A
TA = 25°C
ns
38
21
SN54HC573A
TA = 25°C
VCC = 2 V
30
45
SN74HC573A
VCC = 6 V
150
SN54HC573A
TA = 25°C
VCC = 4.5 V
30
45
SN74HC573A
VCC = 2 V
35
SN74HC573A
TA = 25°C
ns
220
27
SN54HC573A
TA = 25°C
VCC = 6 V
175
265
SN74HC573A
TA = 25°C
30
45
SN74HC573A
tpd
35
SN54HC573A
TA = 25°C
VCC = 6 V
UNIT
21
ns
26
SN54HC573A
38
SN74HC573A
32
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over operating free-air temperature range (unless otherwise noted; see Figure 7-1)
PARAMETER
TEST CONDITIONS
MIN
TA = 25°C
VCC = 2 V
CL = 50 pF to any Q (output)
VCC = 4.5 V
60
90
SN74HC573A
75
8
18
SN74HC573A
15
6
SN54HC573A
VCC = 2 V
CL = 150 pF, from D (input)
to Q (output)
13
95
300
250
33
SN54HC573A
TA = 25°C
tpd
60
50
21
51
43
103
SN54HC573A
TA = 25°C
VCC = 4.5 V
285
33
ten
CL = 150 pF, from OE (input)
to any Q (output)
67
57
29
SN54HC573A
60
50
85
300
250
29
SN54HC573A
TA = 25°C
60
CL = 150 pF to any Q (output)
VCC = 4.5 V
51
43
60
SN54HC573A
8
210
315
265
17
42
SN54HC573A
63
SN74HC573A
53
TA = 25°C
VCC = 6 V
34
SN74HC573A
TA = 25°C
14
ns
36
SN54HC573A
53
SN74HC573A
45
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ns
50
26
SN74HC573A
tt
40
SN54HC573A
TA = 25°C
VCC = 2 V
200
SN74HC573A
SN74HC573A
VCC = 6 V
40
SN54HC573A
TA = 25°C
VCC = 4.5 V
45
SN74HC573A
TA = 25°C
ns
335
SN74HC573A
VCC = 2 V
225
SN54HC573A
TA = 25°C
VCC = 6 V
34
SN74HC573A
SN74HC573A
CL = 150 pF, from LE (input) to
any Q (output)
40
SN54HC573A
TA = 25°C
VCC = 2 V
200
SN74HC573A
SN74HC573A
VCC = 6 V
10
SN54HC573A
TA = 25°C
VCC = 4.5 V
ns
15
SN74HC573A
TA = 25°C
UNIT
12
SN54HC573A
TA = 25°C
VCC = 6 V
MAX
28
SN54HC573A
TA = 25°C
tt
TYP
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6.8 Typical Characteristics
250
CL 50pF
CL 150pF
225
TPD Max(ns)
200
175
150
125
100
75
50
25
2
2.5
3
3.5
4
Vcc
4.5
5
5.5
6
D001
Figure 6-1. Maximum Propagation Delay Curves
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7 Parameter Measurement Information
VCC
PARAMETER
S1
Test
Point
From Output
Under Test
ten
RL
tPZH
RL
CL
50 pF
or
150 pF
1 kΩ
tPZL
tdis
S2
tPLZ
1 kΩ
50 pF
−−
50 pF
or
150 pF
tpd or tt
LOAD CIRCUIT
50%
Data
50%
Input 10%
VCC
50%
50%
50%
tPLH
50%
10%
tPHL
90%
90%
tr
tPHL
90%
tPZL
Output
Waveform 1
(See Note B)
VOH
tPZH
tPLH
50%
10%
tf
50%
10%
C.
D.
E.
F.
G.
Output
Control
(Low-Level
Enabling)
VOH
50%
10% V
OL
tf
90%
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
A.
B.
Open
Open
Open
th
90%
90%
VCC
50%
10% 0 V
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
0V
Out-ofPhase
Output
Closed
tr
0V
VCC
In-Phase
Output
Closed
0V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Open
Open
tsu
0V
50%
Closed
50%
50%
tw
Low-Level
Pulse
Open
VCC
Reference
Input
VCC
High-Level
Pulse
S2
Closed
tPHZ
CL
(see Note A)
S1
VCC
50%
50%
0V
tPLZ
≈VCC
≈VCC
50%
10%
VOL
tPHZ
Output
Waveform 2
(See Note B)
50%
90%
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
CL includes probe and test-fixture capacitance.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
The outputs are measured one at a time with one input transition per measurement.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
tPLH and tPHL are the same as tpd.
Figure 7-1. Load Circuit and Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically
for driving highly capacitive or relatively low-impedance loads. A buffered output-enable ( OE) input can be used
to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In
the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state
and increased drive provide the capability to drive bus lines without interface or pullup components.
To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
8.2 Functional Block Diagram
OE
LE
1
11
C1
1D
2
19
1Q
1D
To Seven Other Channels
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. Logic Diagram (Positive Logic)
8.3 Feature Description
The SNx4HC573A is a high current 3-state output device which can drive bus lines directly or up to 15 LSTTL
loads. It has low power consumption up to 80-µA maximum ICC. The high speed CMOS family has typical
propagation delay of 21 ns with ±6-mA output drive at 5 V. The input leakage current is a very low 1-µA
(maximum).
8.4 Device Functional Modes
Table 8-1 lists the functional modes of the SNx4HC573A.
Table 8-1. Function Table (Each Latch)
INPUTS
OE
OUTPUT
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Hi-Z
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does
not affect the internal operations of the latches. Old data can be retained or new data can be entered while the
outputs are in the high-impedance state. The SNx4HC573A latches can be used to store 8 bits of data. Figure
9-1 shows a typical application. A low trigger event latches the output to preserve the event for processing later.
With latch input high, this acts as a buffer which follows the live data at the D input when output enable pin held
is low.
9.2 Typical Application
Run/Trigger
LE
Enable
OE
Live Data
Q
Output
D
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Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements
The SNx4HC573A device uses CMOS technology and has balanced output drive (±7.8-mA). Take care to avoid
bus contention, because it can drive currents that would exceed maximum limits.
9.2.2 Detailed Design Procedure
Design requirements must adhere to the Section 6.3 and must never exceed the Section 6.1.
The inputs must have a ramp time less than input transition time mentioned in the Section 6.3. Slow inputs can
cause oscillations at the output, false triggering, and increased current consumption. TI recommends a Schmitt
trigger device like SN74HC14 which can tolerate slower signals.
The inputs and outputs must never exceed VCC to not forward bias the internal ESD diodes. The maximum
frequency supported by this device is 28 MHz.
12
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Product Folder Links: SN54HC573A SN74HC573A
SN54HC573A, SN74HC573A
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SCLS147G – DECEMBER 1982 – REVISED APRIL 2022
9.2.3 Application Curve
100
CL 50pF
CL 150pF
90
TPD typ (ns)
80
70
60
50
40
30
20
2
2.5
3
3.5
4
Vcc
4.5
5
5.5
6
D001
Figure 9-2. Typical Propagation Delay Curves
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Section 6.3 table. The total current through Ground or VCC must not exceed ±70 mA as per Section 6.1 table.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends 0.1-µF capacitor; if there are multiple VCC pins, then TI recommends 0.01-µF or
0.022-µF capacitor for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different
frequencies of noise. A 0.1-µF and 1-µF capacitor are commonly used in parallel. The bypass capacitor must be
installed as close to the power pin as possible for best results.
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13
SN54HC573A, SN74HC573A
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SCLS147G – DECEMBER 1982 – REVISED APRIL 2022
11 Layout
11.1 Layout Guidelines
When using multiple-bit logic devices, inputs must never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input and the gate are used, or only 3 of the 4 buffer gates are used. Such input pins must not
be left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 11-1 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally, they are tied to GND or
VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs, unless the part is a
transceiver. If the transceiver has an output enable pin, it disables the output section of the part when asserted.
This does not disable the input section of the I/Os, so they cannot float when disabled.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 11-1. Layout Diagram
14
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SN54HC573A, SN74HC573A
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SCLS147G – DECEMBER 1982 – REVISED APRIL 2022
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54HC573A
Click here
Click here
Click here
Click here
Click here
SN74HC573A
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN54HC573A SN74HC573A
15
PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-8512801VRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8512801VR
A
SNV54HC573AJ
85128012A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
85128012A
SNJ54HC
573AFK
8512801RA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8512801RA
SNJ54HC573AJ
Samples
8512801SA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8512801SA
SNJ54HC573AW
Samples
JM38510/65406BRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65406BRA
Samples
M38510/65406BRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65406BRA
Samples
SN54HC573AJ
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SN54HC573AJ
Samples
SN74HC573ADBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC573A
Samples
SN74HC573ADW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC573A
Samples
SN74HC573ADWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC573A
Samples
SN74HC573ADWRG4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC573A
Samples
SN74HC573AN
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC573AN
Samples
SN74HC573ANE4
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC573AN
Samples
SN74HC573APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC573A
Samples
SN74HC573APWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC573A
Samples
SN74HC573APWT
ACTIVE
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC573A
Samples
SNJ54HC573AFK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
85128012A
SNJ54HC
573AFK
Addendum-Page 1
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
19-Nov-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
SNJ54HC573AJ
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8512801RA
SNJ54HC573AJ
Samples
SNJ54HC573AW
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8512801SA
SNJ54HC573AW
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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