SN74HC573AQPWRQ1

SN74HC573A-Q1 SCLS600C – NOVEMBER 2004 – REVISED JUNE 2022 SN74HC573A-Q1 Octal Transparent D-Type Latch With 3-State Outputs 1 Features 2 Description • • • This octal transparent D-type latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. • • • • • Qualified for automotive applications Wide operating voltage range of 2 V to 6 V High-current 3-state outputs drive bus lines directly or up to 15 LSTTL loads Low power consumption, 80-μA max ICC Typical tpd = 21 ns ±6-mA output drive at 5 V Low input current of 1 μA max Bus-structured pinout Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74HC573AQDW-Q1 SOIC (20) 12.80 mm × 7.50 mm SN74HC573AQPW-Q1 TSSOP (20) 6.50 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74HC573A-Q1 www.ti.com SCLS600C – NOVEMBER 2004 – REVISED JUNE 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings ....................................... 4 5.2 Recommended Operating Conditions(1) .................... 4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Timing Requirements.................................................. 5 5.6 Switching Characteristics ...........................................6 5.7 Switching Characteristics............................................6 5.8 Operating Characteristics........................................... 6 6 Parameter Measurement Information............................ 7 7 Detailed Description........................................................8 7.1 Overview..................................................................... 8 7.2 Functional Block Diagram........................................... 8 7.3 Device Functional Modes............................................8 8 Power Supply Recommendations..................................9 9 Layout...............................................................................9 9.1 Layout Guidelines....................................................... 9 10 Device and Documentation Support..........................10 10.1 Receiving Notification of Documentation Updates..10 10.2 Support Resources................................................. 10 10.3 Trademarks............................................................. 10 10.4 Electrostatic Discharge Caution..............................10 10.5 Glossary..................................................................10 11 Mechanical, Packaging, and Orderable Information.................................................................... 10 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (February 2022) to Revision C (June 2022) Page • Junction-to-ambient thermal resistance values increased. DW was 58 is now 109.1, PW was 83 is now 131.8 ............................................................................................................................................................................4 Changes from Revision A (April 2008) to Revision B (February 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74HC573A-Q1 SN74HC573A-Q1 www.ti.com SCLS600C – NOVEMBER 2004 – REVISED JUNE 2022 4 Pin Configuration and Functions OE 1 20 VCC 1D 2 19 1Q 2D 3 18 2Q 3D 4 17 3Q 4D 5 16 4Q 5D 6 15 5Q 6D 7 14 6Q 7D 8 13 7Q 8D 9 12 8Q 10 11 LE GND DW or PW Package 20-Pin SOIC or TSSOP Top View Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74HC573A-Q1 3 SN74HC573A-Q1 www.ti.com SCLS600C – NOVEMBER 2004 – REVISED JUNE 2022 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC Supply voltage range current(2) MIN MAX –0.5 7 UNIT V IIK Input clamp VI < 0 or VI > VCC ±20 mA IOK Output clamp current(2) VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±35 mA ±70 mA 150 ℃ 150 ℃ Continuous current through VCC or GND TJ Junction temperature Tstg Storage temperature range (1) (2) –65 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 5.2 Recommended Operating Conditions(1) VCC Supply voltage VIH High-level input voltage VCC = 2 V MIN NOM MAX 2 5 6 V 3.15 4.2 VCC = 2 V Low-level input voltage V 1.5 VCC = 4.5 V VCC = 6 V VIL UNIT 0.5 VCC = 4.5 V 1.35 VCC = 6 V V 1.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V tt Input transition (rise and fall) time TA Operating free-air temperature VCC = 2 V 1000 VCC = 4.5 V VCC = 6 V (1) ns 500 400 −40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5.3 Thermal Information THERMAL METRIC PW (TSSOP) 20 PINS 20 PINS UNIT 109.1 131.8 °C/W 76 72.2 °C/W RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance 77.6 82.8 °C/W ψJT Junction-to-top characterization parameter 51.5 21.5 °C/W ψJB Junction-to-board characterization parameter 77.1 82.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) 4 (1) DW (SOIC) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74HC573A-Q1 SN74HC573A-Q1 www.ti.com SCLS600C – NOVEMBER 2004 – REVISED JUNE 2022 5.4 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 μA VOH TYP 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 IOH = −7.8 mA VOL IOZ VO = VCC or 0 ICC VI = VCC or 0, MAX MIN UNIT MAX V 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 6V ±0.01 ±0.5 ±10 ±5 μA 8 160 80 μA 10 10 10 pF IOL = 7.8 mA VI = VCC or 0 MIN IOL = 20 μA VI = VIH or VIL II MAX TA = −40°C to 85°C MIN VI = VIH or VIL IOH = −6 mA TA = −40°C to 125°C TA = 25°C VCC IO = 0 Ci 6V 2 V to 6 V 3 V 5.5 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) VCC tw tsu th Pulse duration, LE high Setup time, data before LE↓ Hold time, data after LE ↓ TA = 25°C MIN TA = −40°C to 125°C MAX MIN MAX TA = −40°C to 85°C MIN 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 50 75 63 4.5 V 10 15 13 6V 9 13 11 2V 20 24 24 4.5 V 5 5 5 6V 5 5 5 MAX UNIT ns ns ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74HC573A-Q1 5 SN74HC573A-Q1 www.ti.com SCLS600C – NOVEMBER 2004 – REVISED JUNE 2022 5.6 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 6-1) PARAMETER FROM (INPUT) TO (OUTPUT) D Q tpd LE ten tdis Any Q OE Any Q OE Any Q tt Any Q TA = −40°C to 125°C TA = 25°C VCC MIN MIN TA = −40°C to 85°C MAX MIN UNIT TYP MAX MAX 2V 77 175 265 220 4.5 V 26 35 53 44 6V 23 30 45 38 2V 87 175 265 260 4.5 V 27 35 53 44 6V 23 30 45 38 2V 68 150 225 190 4.5 V 24 30 45 38 6V 21 26 38 32 2V 47 150 225 190 4.5 V 23 30 45 38 6V 21 26 38 32 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 ns ns ns ns 5.7 Switching Characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 6-1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC D Q tpd LE ten Any Q OE Any Q tt Any Q TA = −40°C to 125°C TA = 25°C MIN MIN TA = −40°C to 85°C MAX MIN UNIT TYP MAX MAX 2V 95 200 300 250 4.5 V 33 40 60 50 6V 21 34 51 43 2V 103 225 335 285 4.5 V 33 45 67 57 6V 29 38 57 48 2V 85 200 300 250 4.5 V 29 40 60 50 6V 26 34 51 43 2V 60 210 315 265 4.5 V 17 42 63 53 6V 14 36 53 45 ns ns ns 5.8 Operating Characteristics TA = 25℃ PARAMETER Cpd 6 TEST CONDITIONS Power dissipation capacitance per latch No load Submit Document Feedback TYP 50 UNIT pF Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74HC573A-Q1 SN74HC573A-Q1 www.ti.com SCLS600C – NOVEMBER 2004 – REVISED JUNE 2022 6 Parameter Measurement Information A. B. C. D. E. F. G. CL includes probe and test-fixture capacitance. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. The outputs are measured one at a time, with one input transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. tPLH and tPHL are the same as tpd. Figure 6-1. Load Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74HC573A-Q1 7 SN74HC573A-Q1 www.ti.com SCLS600C – NOVEMBER 2004 – REVISED JUNE 2022 7 Detailed Description 7.1 Overview This octal transparent D-type latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. 7.2 Functional Block Diagram 7.3 Device Functional Modes Table 7-1. Function Table (Each Latch) INPUTS 8 OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74HC573A-Q1 SN74HC573A-Q1 www.ti.com SCLS600C – NOVEMBER 2004 – REVISED JUNE 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74HC573A-Q1 9 SN74HC573A-Q1 www.ti.com SCLS600C – NOVEMBER 2004 – REVISED JUNE 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74HC573A-Q1 PACKAGE OPTION ADDENDUM www.ti.com 1-Jul-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74HC573AQDWRQ1 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HC573AQ Samples SN74HC573AQPWRG4Q1 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HC573AQ Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of