SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151E – DECEMBER 1982 – REVISED MARCH 2003
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
High-Current 3-State Outputs Can Drive Up
To 15 LSTTL Loads
Low Power Consumption, 80-µA Max ICC
Typical tpd = 11 ns
±6-mA Output Drive at 5 V
D
D
Low Input Current of 1 µA Max
Independent Registers and Enables for
A and B Buses
Multiplexed Real-Time and Stored Data
True Data Paths
SN54HC652 . . . JT OR W PACKAGE
SN74HC652 . . . DW OR NT PACKAGE
(TOP VIEW)
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
OEAB
SAB
CLKAB
NC
VCC
CLKBA
SBA
1
VCC
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
NC
A4
A5
A6
5
4
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
19
11
12 13 14 15 16 17 18
OEBA
B1
B2
NC
B3
B4
B5
A7
A8
GND
NC
B8
B7
B6
CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
SN54HC652 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
description/ordering information
The ’HC652 devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable
(OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs
are provided to select real-time or stored-data transfer. A low input level selects real-time data, and a high input
level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be
performed with these devices.
ORDERING INFORMATION
PDIP – NT
–40°C to 85°C
–55°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
Tube
SN74HC652NT
Tube
SN74HC652DW
Tape and reel
SN74HC652DWR
CDIP – JT
Tube
SNJ54HC652JT
SNJ54HC652JT
CFP – W
Tube
SNJ54HC652W
SNJ54HC652W
LCCC – FK
Tube
SNJ54HC652FK
SNJ54HC652FK
SOIC – DW
SN74HC652NT
HC652
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151E – DECEMBER 1982 – REVISED MARCH 2003
description/ordering information (continued)
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When
SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.
When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor, and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking/current-sourcing capability of the driver.
FUNCTION TABLE
DATA I/O†
INPUTS
OPERATION OR FUNCTION
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
A1–A8
B1–B8
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
↑
↑
X
X
Input
H
↑
H or L
X
Input
H
H
↑
↑
X
X‡
Input
Unspecified‡
Store A and B data
X
X
Input
Output
Store A in both registers
L
X
H or L
↑
X
Unspecified‡
Input
Hold A, store B
L
L
↑
↑
X
X
X‡
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
Output
Stored A data to B bus and
stored B data to A bus
H
L
H or L
H or L
H
H
Output
Store A, hold B
† The data-output functions are enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are enabled;
i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
‡ Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
3
21
OEAB OEBA
L
L
1
23
2
CLKAB CLKBA SAB
X
X
X
BUS B
BUS A
BUS A
BUS B
SCLS151E – DECEMBER 1982 – REVISED MARCH 2003
22
SBA
L
3
21
OEAB OEBA
H
H
21
OEBA
H
X
H
1
23
2
CLKAB CLKBA SAB
↑
X
↑
X
↑
↑
X
X
X
2
SAB
L
22
SBA
X
BUS B
BUS A
BUS A
3
OEAB
X
L
L
23
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
1
CLKAB
X
22
3
21
1
23
2
22
SBA
OEAB
H
OEBA
L
CLKAB
CLKBA
SAB
SBA
H or L
H or L
H
H
X
X
X
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Pin numbers shown are for the DW, JT, NT, and W packages.
Figure 1. Bus-Management Functions
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3
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151E – DECEMBER 1982 – REVISED MARCH 2003
logic diagram (positive logic)
OEBA
OEAB
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
One of Eight Channels
1D
C1
A1
4
20
B1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DW, JT, NT, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
(see Note 3): NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-3.
4
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SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151E – DECEMBER 1982 – REVISED MARCH 2003
recommended operating conditions (see Note 4)
SN54HC652
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 4.5 V
High-level input voltage
VCC = 6 V
VCC = 2 V
VIL
VI
VO
tt
Low-level input voltage
NOM
MAX
2
5
6
MAX
2
5
6
3.15
3.15
4.2
4.2
0
UNIT
V
V
0.5
0.5
1.35
1.35
1.8
1.8
VCC
VCC
VCC = 2 V
VCC = 4.5 V
Input transition (rise and fall) time
NOM
1.5
0
Output voltage
MIN
1.5
VCC = 4.5 V
VCC = 6 V
Input voltage
SN74HC652
MIN
0
VCC
VCC
0
1000
1000
500
500
V
V
V
ns
VCC = 6 V
400
400
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
IOZ
ICC
Ci
A or B
SN54HC652
MIN
MAX
SN74HC652
MIN
MAX
UNIT
2V
1.9
1.998
1.9
1.9
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
IOH = –6 mA
IOH = –7.8 mA
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
5.34
2V
0.002
0.1
0.1
0.1
IOL = 20 µA
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
VI = VCC or 0
6V
±0.1
±100
±1000
±1000
nA
VO = VCC or GND
VI = VCC or 0,
IO = 0
6V
±0.01
±0.5
±10
±5
µA
8
160
80
µA
10
10
10
pF
IOL = 6 mA
IOL = 7.8 mA
II
TA = 25°C
TYP
MAX
4.5 V
VI = VIH or VIL
Control
inputs
MIN
IOH = –20 µA
VI = VIH or VIL
VOL
VCC
Control
inputs
6V
2 V to 6 V
3
V
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151E – DECEMBER 1982 – REVISED MARCH 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
fclock
Clock frequency
tw
Pulse duration, CLKBA or CLKAB high or low
Setup time, A before CLKAB↑
↑ or B before CLKBA↑
↑
tsu
Hold time, A after CLKAB↑
↑ or B after CLKBA↑
↑
th
TA = 25°C
MIN
MAX
SN54HC652
MIN
MAX
SN74HC652
MIN
MAX
2V
6
4.3
5.5
4.5 V
31
22
27
6V
36
25
31
2V
80
115
95
4.5 V
16
23
19
6V
14
20
16
2V
100
150
125
4.5 V
20
30
25
6V
17
26
21
2V
5
5
5
4.5 V
5
5
5
6V
5
5
5
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
CLKBA or CLKAB
tpd
A or B
SBA or SAB†
ten
tdis
OEBA or OEAB
OEBA or OEAB
tt
A or B
B or A
A or B
A or B
A or B
Any
VCC
TA = 25°C
MIN
TYP
MAX
SN54HC652
MIN
MAX
MIN
2V
6
10
4.3
5.5
4.5 V
31
40
22
27
6V
36
45
25
MAX
31
65
180
270
225
4.5 V
18
36
54
45
6V
14
31
46
38
2V
50
135
205
170
4.5 V
14
27
41
34
6V
11
23
35
29
2V
70
190
285
240
4.5 V
20
38
57
48
6V
16
32
48
41
2V
85
245
370
305
4.5 V
25
49
74
61
6V
20
42
63
52
2V
50
245
370
305
4.5 V
23
49
74
61
6V
20
42
63
52
2V
28
60
90
75
4.5 V
8
12
18
15
6V
6
10
15
13
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MHz
2V
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
6
SN74HC652
ns
ns
ns
ns
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151E – DECEMBER 1982 – REVISED MARCH 2003
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 2)
PARAMETER
tpd
SN54HC652
SN74HC652
TO
(OUTPUT)
VCC
2V
90
265
400
330
CLKBA or CLKAB
A or B
4.5 V
24
53
80
66
6V
18
46
68
57
A or B
B or A
SBA or SAB†
ten
TA = 25°C
TYP
MAX
FROM
(INPUT)
A or B
OEBA or OEAB
A or B
tt
Any
MIN
MIN
MAX
MIN
MAX
2V
70
220
335
275
4.5 V
20
44
70
55
6V
15
38
57
48
2V
80
275
415
345
4.5 V
24
55
83
69
6V
20
47
70
60
2V
100
330
500
410
4.5 V
33
66
100
82
6V
27
57
85
71
2V
45
210
315
265
4.5 V
17
42
63
53
6V
13
36
53
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
UNIT
ns
ns
ns
43
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load
TYP
50
UNIT
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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• DALLAS, TEXAS 75265
7
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151E – DECEMBER 1982 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
CL
(see Note A)
PARAMETER
S1
Test
Point
tPZH
ten
RL
1 kΩ
tPZL
tPHZ
tdis
S2
RL
1 kΩ
Data
Input
VCC
50%
10%
50%
50%
0V
In-Phase
Output
50%
10%
tPHL
90%
90%
tr
tPHL
Out-ofPhase
Output
90%
tf
Closed
Closed
Open
Open
Open
VCC
th
90%
90%
VCC
50%
10% 0 V
tf
50%
10%
Output
Control
(Low-Level
Enabling)
VCC
50%
50%
0V
tPZL
VOH
50%
10% V
OL
tf
Output
Waveform 1
(See Note B)
tPLZ
90%
VOH
VOL
Output
Waveform 2
(See Note B)
≈VCC
≈VCC
50%
10%
tPZH
tPLH
50%
10%
Open
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VCC
tPLH
Open
tr
VOLTAGE WAVEFORMS
PULSE DURATIONS
50%
Closed
0V
0V
Input
Closed
tsu
0V
50%
Open
50%
50%
tw
Low-Level
Pulse
50 pF
or
150 pF
50 pF
or
150 pF
––
Reference
Input
VCC
S2
50 pF
LOAD CIRCUIT
50%
S1
tPLZ
tpd or tt
High-Level
Pulse
CL
VOL
tPHZ
50%
90%
VOH
≈0 V
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74HC652DW
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC652
SN74HC652DWR
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC652
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of