SN54HC86, SN74HC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 20-µA Max ICC
Typical tpd = 10 ns
D
D
D
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
True Logic
SN54HC86 . . . J OR W PACKAGE
SN74HC86 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
9
7
8
1B
1A
NC
VCC
4B
VCC
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
NC
2B
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
1A
1B
1Y
2A
2B
2Y
GND
SN54HC86 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
description/ordering information
These devices contain four independent 2-input exclusive-OR gates. They perform the Boolean function
Y=A
B or Y = AB + AB in positive logic.
ę
A common application is as a true / complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
ORDERING INFORMATION
PACKAGE†
TA
PDIP – N
SN74HC86N
Tube of 50
SN74HC86D
Reel of 2500
SN74HC86DR
Reel of 250
SN74HC86DT
Reel of 2000
SN74HC86NSR
Tube of 90
SN74HC86PW
Reel of 2000
SN74HC86PWR
Reel of 250
SN74HC86PWT
CDIP – J
Tube of 25
SNJ54HC86J
SNJ54HC86J
CFP – W
Tube of 150
SNJ54HC86W
SNJ54HC86W
LCCC – FK
Tube of 55
SNJ54HC86FK
SOP – NS
TSSOP – PW
–55 C to 125
–55°C
125°C
C
TOP-SIDE
MARKING
Tube of 25
SOIC – D
C
–40°C
–40
C to 85
85°C
ORDERABLE
PART NUMBER
SN74HC86N
HC86
HC86
HC86
SNJ54HC86FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54HC86, SN74HC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
L
L
L
L
H
H
H
L
H
H
H
L
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
Exclusive OR
=1
These are five equivalent exclusive-OR symbols valid for an ’HC86 gate in positive logic; negation may be
shown at any two ports.
Logic Identity Element
Even-Parity Element
=
2k
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
Odd-Parity Element
2k + 1
The output is active (high) if
an odd number of inputs (i.e.,
only 1 of the 2) are active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54HC86, SN74HC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HC86
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 4.5 V
High-level input voltage
VCC = 6 V
VCC = 2 V
VIL
Low-level input voltage
VI
VO
MAX
2
5
6
NOM
MAX
2
5
6
1.5
3.15
3.15
4.2
4.2
0
UNIT
V
V
0.5
0.5
1.35
1.35
1.8
1.8
VCC
VCC
VCC = 2 V
VCC = 4.5 V
Input transition rise/fall time
MIN
1.5
0
Output voltage
∆t/∆v
t/ v
NOM
VCC = 4.5 V
VCC = 6 V
Input voltage
SN74HC86
MIN
0
VCC
VCC
0
1000
1000
500
500
V
V
V
ns
VCC = 6 V
400
400
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
VCC
Ci
SN54HC86
SN74HC86
MIN
MIN
MAX
MAX
UNIT
2V
1.9
1.998
1.9
1.9
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
IOH = –4 mA
IOH = –5.2 mA
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
5.34
2V
0.002
0.1
0.1
0.1
IOL = 20 µA
A
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
2
40
20
µA
3
10
10
10
pF
VI = VIH or VIL
VI = VIH or VIL
VI = VCC or 0
VI = VCC or 0,
TA = 25°C
TYP
MAX
IOH = –20 µA
A
IOL = 4 mA
IOL = 5.2 mA
II
ICC
MIN
IO = 0
6V
2 V to 6 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
V
3
SN54HC86, SN74HC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
MAX
SN54HC86
SN74HC86
MIN
MIN
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
40
100
150
125
tpd
A or B
Y
4.5 V
12
20
30
25
6V
10
17
25
21
tt
Y
MIN
MAX
MAX
2V
28
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
UNIT
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
No load
TYP
UNIT
35
pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
Input
VCC
50%
50%
0V
CL = 50 pF
(see Note A)
tPLH
In-Phase
Output
LOAD CIRCUIT
50%
10%
tPHL
90%
90%
tr
Input
50%
10%
90%
90%
tr
tPHL
VCC
50%
10% 0 V
Out-of-Phase
Output
90%
tf
VOH
50%
10%
VOL
tf
tPLH
50%
10%
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
84046012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84046012A
SNJ54HC
86FK
8404601CA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8404601CA
SNJ54HC86J
8404601DA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8404601DA
SNJ54HC86W
JM38510/65202BCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65202BCA
M38510/65202BCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65202BCA
SN54HC86J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54HC86J
SN74HC86D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC86
SN74HC86DE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC86
SN74HC86DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC86
SN74HC86DT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC86
SN74HC86N
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC86N
SN74HC86NE4
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC86N
SN74HC86NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC86
SN74HC86NSRE4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC86
SN74HC86NSRG4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC86
SN74HC86PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC86
SN74HC86PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC86
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SNJ54HC86FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84046012A
SNJ54HC
86FK
SNJ54HC86J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8404601CA
SNJ54HC86J
SNJ54HC86W
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8404601DA
SNJ54HC86W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
