SN74HC86PWT

SN74HC86, SN54HC86 SN54HC86 SCLS100F – DECEMBERSN74HC86, 1982 – REVISED APRIL 2021 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 www.ti.com SNx4HC86 Quadruple 2-Input XOR Gates 1 Features 3 Description • • • This device contains four independent 2-input XOR gates. Each gate performs the Boolean function Y = A ⊕ B in positive logic. • • Buffered inputs Wide operating voltage range: 2 V to 6 V Wide operating temperature range: –40°C to +85°C Supports fanout up to 10 LSTTL loads Significant power reduction compared to LSTTL logic ICs 2 Applications • • Detect phase differences in input signals Create a selectable inverter / buffer Device Information(1) PART NUMBER 1B 1Y 2A 2B 2Y GND BODY SIZE (NOM) SN74HC86D SOIC (14) 8.70 mm × 3.90 mm SN74HC86N PDIP (14) 19.30 mm × 6.40 mm SN74HC86NS SO (14) 10.20 mm × 5.30 mm SN74HC86PW TSSOP (14) 5.00 mm × 4.40 mm SN54HC86J CDIP (14) 21.30 mm × 7.60 mm SN54HC86W CFP (14) 9.20 mm × 6.29 mm SN54HC86FK LCCC (20) 8.90 mm × 8.90 mm (1) 1A PACKAGE For all available packages, see the orderable addendum at the end of the data sheet. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y Functional pinout An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2021 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: SN74HC86 SN54HC86 1 SN74HC86, SN54HC86 www.ti.com SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 Pin Functions.................................................................... 3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 Recommended Operating Conditions.........................4 6.3 Thermal Information....................................................4 6.4 Electrical Characteristics - 74..................................... 5 6.5 Electrical Characteristics - 54..................................... 5 6.6 Switching Characteristics - 74.....................................6 6.7 Switching Characteristics - 54.....................................6 6.8 Operating Characteristics........................................... 6 6.9 Typical Characteristics................................................ 6 7 Parameter Measurement Information............................ 8 8 Detailed Description........................................................9 8.1 Overview..................................................................... 9 8.2 Functional Block Diagram........................................... 9 8.3 Feature Description.....................................................9 8.4 Device Functional Modes..........................................10 9 Application and Implementation.................................. 11 9.1 Application Information..............................................11 9.2 Typical Application.................................................... 11 10 Power Supply Recommendations..............................13 11 Layout........................................................................... 13 11.1 Layout Guidelines................................................... 13 11.2 Layout Example...................................................... 13 12 Device and Documentation Support..........................14 12.1 Documentation Support.......................................... 14 12.2 Related Links.......................................................... 14 12.3 Support Resources................................................. 14 12.4 Trademarks............................................................. 14 12.5 Electrostatic Discharge Caution..............................14 12.6 Glossary..................................................................14 13 Mechanical, Packaging, and Orderable Information.................................................................... 14 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (August 2003) to Revision F (April 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated to new data sheet standards................................................................................................................ 1 • Increased D (86 to 133.6), NS (76 to 122.6), and PW (113 to 151.7); decreased N (80 to 62.8) °C/W............. 4 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HC86 SN54HC86 SN74HC86, SN54HC86 www.ti.com SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 5 Pin Configuration and Functions 1B 1A NC VCC 4B 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 1Y 4 3 2 1 20 19 18 4A NC 5 17 NC 4Y 2A 4 11 4Y 2B 5 10 3B 2A 6 16 2Y 6 9 3A NC 7 15 NC GND 7 8 3Y 2B 8 14 9 10 11 12 13 3B Figure 5-1. D, N, NS, PW, J, or W Package 14-Pin SOIC, PDIP, SO, TSSOP, CDIP, or CFP Top View 2Y GND NC 3Y 3A Figure 5-2. FK Package 20-Pin LCCC Top View Pin Functions PIN D, N, NS, PW, J, or W FK 1A 1 2 1B 2 1Y 3 2A 2B 2Y GND NAME I/O DESCRIPTION Input Channel 1, Input A 3 Input Channel 1, Input B 4 Output 4 6 Input Channel 2, Input A 5 8 Input Channel 2, Input B 6 9 Output 7 10 — 3Y 8 12 Output 3A 9 13 Input Channel 3, Input A 3B 10 14 Input Channel 3, Input B 4Y 11 16 Output 4A 12 18 Input Channel 4, Input A 4B 13 19 Input Channel 4, Input B VCC 14 20 — Positive Supply 1, 5, 7, 11, 15, 17 — Not internally connected NC Channel 1, Output Y Channel 2, Output Y Ground Channel 3, Output Y Channel 4, Output Y Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HC86 SN54HC86 3 SN74HC86, SN54HC86 www.ti.com SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC Supply voltage current(2) MIN MAX –0.5 7 UNIT V IIK Input clamp VI < 0 V or VI > VCC ±20 mA IOK Output clamp current(2) VO < 0 V or VO > VCC ±20 mA Continuous output current VO = 0 to VCC IO Continuous current through VCC or GND TJ Junction temperature(3) Tstg Storage temperature (1) (2) (3) –65 ±25 mA ±50 mA 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Guaranteed by design. 6.2 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC Supply voltage VIH High-level input voltage VCC = 2 V MIN NOM MAX 2 5 6 3.15 VCC = 6 V V 4.2 0.5 VCC = 4.5 V Low-level input voltage V 1.5 VCC = 4.5 V VCC = 2 V VIL UNIT 1.35 VCC = 6 V V 1.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V Δt/Δv Input transition rise and fall rate VCC = 2 V 1000 VCC = 4.5 V 500 VCC = 6 V TA Operating free-air temperature ns 400 SN54HC86 –55 125 SN74HC86 –40 85 °C 6.3 Thermal Information SN74HC86 THERMAL METRIC(1) 4 D (SOIC) N (PDIP) NS (SOP) PW (TSSOP) UNIT 14 PINS 14 PINS 14 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 133.6 62.8 122.6 151.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 89.0 50.5 81.8 79.4 °C/W RθJB Junction-to-board thermal resistance 89.5 42.5 83.8 94.7 °C/W ΨJT Junction-to-top characterization parameter 45.5 30.1 45.4 25.2 °C/W Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HC86 SN54HC86 SN74HC86, SN54HC86 www.ti.com SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 SN74HC86 THERMAL METRIC(1) D (SOIC) N (PDIP) NS (SOP) PW (TSSOP) UNIT 14 PINS 14 PINS 14 PINS 14 PINS ΨJB Junction-to-board characterization parameter 89.1 42.3 83.4 94.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.4 Electrical Characteristics - 74 over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). Operating free-air temperature (TA) PARAMETER VOH High-level output voltage TEST CONDITIONS VI = VIH or VIL IOH = -20 µA Low-level output VI = VIH voltage or VIL 25°C -40°C to 85°C MIN TYP 2V 1.9 1.998 1.9 4.5 V 4.4 4.499 4.4 6V MAX MIN 5.9 5.999 5.9 IOH = -4 mA 4.5 V 3.98 4.3 3.84 IOH = -5.2 mA 6V 5.48 IOL = 20 µA VOL VCC 5.8 2V 0.002 TYP UNIT MAX V 5.34 0.1 0.1 4.5 V 0.001 0.1 0.1 IOL = 20 µA 6V 0.001 0.1 0.1 IOL = 4 mA 4.5 V 0.17 0.26 0.33 IOL = 5.2 mA 6V 0.15 0.26 0.33 ±0.1 ±100 ±1000 nA 2 20 µA 10 10 pF II Input leakage current VI = VCC or 0 6V ICC Supply current VI = VCC or 0 6V Ci Input capacitance IO = 0 2 V to 6 V 3 V 6.5 Electrical Characteristics - 54 over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). Operating free-air temperature (TA) PARAMETER TEST CONDITIONS IOH = –20 µA VOH High-level output voltage VI = VIH or IOH = –4 VIL mA VOL Low-level output VI = VIH or voltage VIL –40°C to 85°C MAX MIN TYP –55°C to 125°C MIN TYP 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 3.98 4.3 3.84 3.7 MAX MIN 5.48 5.8 5.34 5.2 TYP UNIT MAX V 4.5 V IOH = –5.2 6V mA IOL = 20 µA 25°C VCC 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 IOL = 4 mA 4.5 V 0.17 0.26 0.33 0.4 IOL = 5.2 mA 0.15 0.26 0.33 0.4 6V V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HC86 SN54HC86 5 SN74HC86, SN54HC86 www.ti.com SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). Operating free-air temperature (TA) PARAMETER TEST CONDITIONS VCC 25°C MIN –40°C to 85°C TYP MAX MIN TYP –55°C to 125°C MAX MIN TYP UNIT MAX II Input leakage current VI = VCC or 0 6V ±0.1 ±1 ±1 µA ICC Supply current VI = VCC or 0 6V 2 20 40 µA Ci Input capacitance 10 10 10 pF IO = 0 2 V to 6V 3 6.6 Switching Characteristics - 74 over operating free-air temperature range (unless otherwise noted) Operating free-air temperature (TA) PARAMETER FROM TO VCC 25°C MIN tpd tt Propagation delay A or B Y Transition-time Y –40°C to 85°C MIN TYP UNIT TYP MAX MAX 2V 40 100 125 4.5 V 12 20 25 6V 10 17 21 2V 28 75 95 4.5 V 8 15 19 6V 6 13 16 ns ns 6.7 Switching Characteristics - 54 over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). Operating free-air temperature (TA) PARAMETER FROM TO VCC 25°C MIN tpd tt Propagation delay A or B Transition-time Y Y –40°C to 85°C MIN TYP –55°C to 125°C TYP MAX MAX MIN TYP 2V 40 100 125 150 4.5 V 12 20 25 30 6V 10 17 21 25 2V 38 75 95 110 4.5 V 8 15 19 22 6V 6 13 16 19 UNIT MAX ns ns 6.8 Operating Characteristics over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load per gate VCC 2 V to 6 V MIN TYP 35 MAX UNIT pF 6.9 Typical Characteristics TA = 25°C 6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HC86 SN54HC86 SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 7 0.3 6 0.25 VOL Output Low Voltage (V) VOH Output High Voltage (V) www.ti.com 5 4 3 2 2-V 4.5-V 6-V 1 0 2-V 4.5-V 6-V 0.2 0.15 0.1 0.05 0 0 1 2 3 4 IOH Output High Current (mA) 5 6 Figure 6-1. Typical output voltage in the high state (VOH) 0 1 2 3 4 IOL Output Low Current (mA) 5 6 Figure 6-2. Typical output voltage in the low state (VOL) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HC86 SN54HC86 7 SN74HC86, SN54HC86 www.ti.com SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 7 Parameter Measurement Information • • Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. The outputs are measured one at a time, with one input transition per measurement. Test Point 90% VCC 90% Input 10% 10% tr(1) From Output Under Test CL(1) 0V tf(1) 90% VOH 90% Output 10% A. 10% tr(1) CL= 50 pF and includes probe and jig capacitance. A. Figure 7-1. Load Circuit tf(1) VOL tt is the greater of tr and tf. Figure 7-2. Voltage Waveforms Transition Times VCC Input 50% 50% 0V tPLH (1) tPHL (1) VOH Output 50% 50% VOL tPLH(1) tPHL(1) VOH Output 50% 50% VOL A. The maximum between tPLH and tPHL is used for tpd. Figure 7-3. Voltage Waveforms Propagation Delays 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HC86 SN54HC86 SN74HC86, SN54HC86 www.ti.com SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 8 Detailed Description 8.1 Overview This device contains four independent 2-input XOR gates. Each gate performs the Boolean function Y = A ⊕ B in positive logic. 8.2 Functional Block Diagram xA xY xB 8.3 Feature Description 8.3.1 Balanced CMOS Push-Pull Outputs A balanced output allows the device to sink and source similar currents. The drive capability of this device may create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to over-current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. The SN74HC86 can drive a load with a total capacitance less than or equal to the maximum load listed in the Switching Characteristics - 74 connected to a high-impedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the provided load value. If larger capacitive loads are required, it is recommended to add a series resistor between the output and the capacitor to limit output current to the values given in the Absolute Maximum Ratings. 8.3.2 Standard CMOS Inputs Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the Electrical Characteristics - 74. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics - 74, using ohm's law (R = V ÷ I). Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the Recommended Operating Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HC86 SN54HC86 9 SN74HC86, SN54HC86 www.ti.com SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 8.3.3 Clamp Diode Structure The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The recommended input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VCC Device +IIK +IOK Logic Input -IIK Output -IOK GND Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output 8.4 Device Functional Modes Table 8-1. Function Table INPUTS A 10 OUTPUT B Y L L L L H H H L H H H L Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HC86 SN54HC86 SN74HC86, SN54HC86 www.ti.com SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information In this application, a 2-input XOR gate is used as a phase difference detector as shown in Figure 9-1. The remaining three gates can be used for other applications in the system, or the inputs can be grounded and the channels left unused. The device is used to identify phase difference between a reference clock and another input clock. Whenever the clock states are different, the XOR output will pulse HIGH until the clocks return to the same state. The output is fed into a low-pass filter to obtain a DC representation of the phase difference. 9.2 Typical Application Input Clock R Output Reference Clo ck C Figure 9-1. Typical application schematic 9.2.1 Design Requirements 9.2.1.1 Power Considerations Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics - 74. The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN74HC86 plus the maximum supply current, ICC, listed in the Electrical Characteristics - 74. The logic device can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. CAUTION The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device. 9.2.1.2 Input Considerations Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the SN74HC86, as specified in the Electrical Characteristics - 74, and the desired input transition rate. A 10-kΩ resistor value is often used due to these factors. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HC86 SN54HC86 11 SN74HC86, SN54HC86 www.ti.com SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 The SN74HC86 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the Recommended Operating Conditions. Refer to Section 8.3 for additional information regarding the inputs for this device. 9.2.1.3 Output Considerations The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the VOH specification in the Electrical Characteristics - 74. Similarly, the ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics - 74. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to Section 8.3 for additional information regarding the outputs for this device. 9.2.2 Detailed Design Procedure 1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in Section 11. 2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC86 to the receiving device. 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in megaohms; much larger than the minimum calculated above. 4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation 9.2.3 Application Curves Reference Clock Input Clock Out Figure 9-2. Typical application timing diagram 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HC86 SN54HC86 SN74HC86, SN54HC86 www.ti.com SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in Figure 11-1. 11 Layout 11.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 11.2 Layout Example GND VCC Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation 0.1 F Avoid 90° corners for signal lines Bypass capacitor placed close to the device 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y Unused inputs tied to VCC Unused output left floating Figure 11-1. Example layout for the SN74HC86 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HC86 SN54HC86 13 SN74HC86, SN54HC86 www.ti.com SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • HCMOS Design Considerations • CMOS Power Consumption and CPD Calculation • Designing with Logic 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HC86 SN54HC86 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 84046012A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 84046012A SNJ54HC 86FK 8404601CA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8404601CA SNJ54HC86J Samples 8404601DA ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8404601DA SNJ54HC86W Samples JM38510/65202BCA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65202BCA Samples M38510/65202BCA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65202BCA Samples SN54HC86J ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN54HC86J Samples SN74HC86D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC86 Samples SN74HC86DE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC86 Samples SN74HC86DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC86 Samples SN74HC86DT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC86 Samples SN74HC86N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC86N Samples SN74HC86NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC86N Samples SN74HC86NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC86 Samples SN74HC86PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC86 Samples SN74HC86PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC86 Samples SNJ54HC86FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 84046012A SNJ54HC 86FK SNJ54HC86J ACTIVE CDIP J 14 1 Non-RoHS & Non-Green SNPB N / A for Pkg Type -55 to 125 8404601CA SNJ54HC86J Addendum-Page 1 Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 15-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) SNJ54HC86W ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8404601DA SNJ54HC86W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of