SN74HCS00DR

SN74HCS00 SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 SN74HCS00 Quadruple 2-Input NAND Gates with Schmitt-Trigger Inputs 1 Features 3 Description • • This device contains four independent 2-input NAND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B in positive logic. • Wide operating voltage range: 2 V to 6 V Schmitt-trigger inputs allow for slow or noisy input signals Low power consumption – Typical ICC of 100 nA – Typical input leakage current of ±100 nA ±7.8-mA output drive at 5 V Extended ambient temperature range: –40°C to +125°C, TA Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) SN74HCS00PW TSSOP (14) 5.00 mm × 4.40 mm SN74HCS00D SOIC (14) 8.70 mm × 3.90 mm SN74HCS00BQA WQFN (14) 3.00 mm × 2.50 mm 2 Applications SN74HCS00DYY SOT-23 (14) 4.20 mm × 2.00 mm • • (1) Alarm or tamper detect circuit S-R latch Voltage Output Current Voltage Current Output Input Voltage Time Output Current Voltage Time Voltage Time Input Voltage Output Response Waveforms Time Time Current Schmitt-trigger CMOS Input Supply Current Response Waveforms Supports Slow Inputs Input Voltage Noise Rejection Input Voltage Standard CMOS Input For all available packages, see the orderable addendum at the end of the data sheet. Input Voltage Input Voltage Waveforms Input Voltage Low Power Supply Current • • Time Benefits of Schmitt-Trigger Inputs An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................5 6.6 Switching Characteristics............................................6 6.7 Typical Characteristics................................................ 7 7 Parameter Measurement Information............................ 8 8 Detailed Description........................................................9 8.1 Overview..................................................................... 9 8.2 Functional Block Diagram........................................... 9 8.3 Feature Description.....................................................9 8.4 Device Functional Modes..........................................10 9 Application and Implementation.................................. 11 9.1 Application Information..............................................11 9.2 Typical Application.................................................... 11 10 Power Supply Recommendations..............................13 11 Layout........................................................................... 14 11.1 Layout Guidelines................................................... 14 11.2 Layout Example...................................................... 14 12 Device and Documentation Support..........................15 12.1 Documentation Support.......................................... 15 12.2 Receiving Notification of Documentation Updates..15 12.3 Support Resources................................................. 15 12.4 Trademarks............................................................. 15 12.5 Electrostatic Discharge Caution..............................15 12.6 Glossary..................................................................15 13 Mechanical, Packaging, and Orderable Information.................................................................... 15 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2021) to Revision C (December 2021) Page • Added DYY package to the Device Information table.........................................................................................1 • Added DYY package information to the Pin Configuration and Functions section............................................. 3 • Added DYY package to Thermal Information table............................................................................................ 5 Changes from Revision A (May 2020) to Revision B (January 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Added BQA package information to Device Information ................................................................................... 1 • Added BQA package information to Pin Configuration and Functions .............................................................. 3 • Added BQA package information to Thermal Information table......................................................................... 5 Changes from Revision * (December 2019) to Revision A (May 2020) Page • Added D package to Device Information table................................................................................................... 1 • Added D package information to Pin Configuration and Functions ................................................................... 3 • Added D package column to Thermal Information table.....................................................................................5 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 5 Pin Configuration and Functions 1A 1 14 VCC 1B 2 13 4B 1Y 2A 3 12 4 11 4A 4Y 2B 5 10 3B 2Y 6 9 GND 7 8 1A VCC 1 14 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 3A 2B 5 10 3B 3Y 2Y 6 9 3A Figure 5-1. D, DYY, or PW Package 14-Pin SOIC, SOT-23, or TSSOP Top View PAD 7 8 GND 3Y Figure 5-2. BQA Package 14-Pin WQFN Top View Table 5-1. Pin Functions PIN NAME NO. I/O DESCRIPTION 1A 1 Input Channel 1, Input A 1B 2 Input Channel 1, Input B 1Y 3 Output 2A 4 Input Channel 2, Input A 2B 5 Input Channel 2, Input B 2Y 6 Output GND 7 — 3Y 8 Output 3A 9 Input Channel 3, Input A 3B 10 Input Channel 3, Input B 4Y 11 Output 4A 12 Input Channel 4, Input A 4B 13 Input Channel 4, Input B VCC 14 — Positive Supply — The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply Thermal Pad(1) (1) Channel 1, Output Y Channel 2, Output Y Ground Channel 3, Output Y Channel 4, Output Y BQA Package only. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 3 SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX –0.5 UNIT VCC Supply voltage IIK Input clamp current(2) VI < –0.5 V or VI > VCC + 0.5 V ±20 7 mA V IOK Output clamp current(2) VO < –0.5 V or VO > VCC + 0.5 V ±20 mA IO Continuous output current VO = 0 to VCC ±35 mA Continuous current through VCC or GND ±70 mA TJ Junction temperature(3) 150 °C Tstg Storage temperature 150 °C (1) (2) (3) –65 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Assured by design. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) 4 MIN NOM 5 VCC Supply voltage 2 VI Input voltage 0 VO Output voltage 0 Δt/Δv Input transition rise and fall rate TA Ambient temperature MAX 6 V VCC V VCC Unlimited –55 Submit Document Feedback UNIT 125 V ns/V °C Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 6.4 Thermal Information SN74HCS00 THERMAL METRIC(1) PW (TSSOP) D (SOIC) BQA (WQFN) DYY (SOT) 14 PINS 14 PINS 14 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal resistance 151.7 133.6 109.7 236.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 79.4 89.0 111.0 143.2 °C/W RθJB Junction-to-board thermal resistance 94.7 89.5 77.9 146.0 °C/W ΨJT Junction-to-top characterization parameter 25.2 45.5 20.2 29.5 °C/W ΨJB Junction-to-board characterization parameter 94.1 89.1 77.8 145.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 56.6 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted). PARAMETER VT+ VT- ΔVT VOH VOL TEST CONDITIONS Positive switching threshold Negative switching threshold Hysteresis (VT+ - VT-) High-level output voltage Low-level output voltage VI = VIH or VIL VI = VIH or VIL VCC MIN TYP MAX UNIT 2V 0.7 1.5 4.5 V 1.7 3.15 6V 2.1 4.2 2V 0.3 1.0 4.5 V 0.9 2.2 6V 1.2 3.0 2V 0.2 1.0 4.5 V 0.4 1.4 6V 0.6 1.6 IOH = -20 µA 2 V to 6 V VCC – 0.1 VCC – 0.002 IOH = -6 mA 4.5 V 4.0 4.3 IOH = -7.8 mA 6V 5.4 IOL = 20 µA 2 V to 6 V IOL = 6 mA IOL = 7.8 mA V V V V 5.75 0.002 0.1 4.5 V 0.18 0.30 6V 0.22 0.33 V II Input leakage current VI = VCC or 0 6V ±100 ±1000 nA ICC Supply current VI = VCC or 0, IO = 0 6V 0.1 2 µA Ci Input capacitance 2 V to 6 V 5 pF Cpd Power dissipation capacitance No load per gate 2 V to 6 V 10 pF Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 5 SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 6.6 Switching Characteristics CL = 50 pF; over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter Measurement Information PARAMETER FROM (INPUT) TO (OUTPUT) VCC TYP MAX 15 36 4.5 V 7 13 6V 5 12 2V 9 16 4.5 V 5 9 6V 4 8 2V tpd tt 6 Propagation delay Transition-time A or B Y Y Submit Document Feedback MIN UNIT ns ns Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 6.7 Typical Characteristics TA = 25°C 70 46 VCC = 2 V VCC = 3.3 V VCC = 4.5 V VCC = 6 V Output Resistance (:) 42 VCC = 2 V VCC = 3.3 V VCC = 4.5 V VCC = 6 V 65 Output Resistance (:) 44 40 38 36 34 32 60 55 50 45 40 30 35 28 26 30 0 2.5 5 7.5 10 12.5 15 17.5 Output Sink Current (mA) 20 22.5 25 Figure 6-1. Output Driver Resistance in Low State 0 ICC ± Supply Current (mA) VCC = 2.5 V 0.14 VCC = 3.3 V ICC ± Supply Current (mA) VCC = 2 V 0.16 0.12 0.1 0.08 0.06 0.04 0.02 0 0 0.5 1 1.5 2 2.5 VI ± Input Voltage (V) 3 3.5 5 7.5 10 12.5 15 17.5 Output Source Current (mA) 20 22.5 25 Figure 6-2. Output Driver Resistance in High State 0.2 0.18 2.5 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 VCC = 4.5 V VCC = 5 V VCC = 6 V 0 0.5 1 1.5 2 2.5 3 3.5 4 VI ± Input Voltage (V) 4.5 5 5.5 6 Figure 6-3. Typical Supply Current vs Input Voltage Figure 6-4. Typical Supply Current vs Input Voltage Across Common Supply Values (2 V to 3.3 V) Across Common Supply Values (4.5 V to 6 V) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 7 SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 7 Parameter Measurement Information • • Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns. The outputs are measured one at a time, with one input transition per measurement. Test Point 90% VCC 90% Input 10% 10% tr(1) From Output Under Test CL(1) 0V tf(1) 90% VOH 90% Output 10% A. 10% tr(1) CL= 50 pF and includes probe and jig capacitance. tf(1) VOL Figure 7-2. Voltage Waveforms Transition Times Figure 7-1. Load Circuit VCC Input 50% 50% 0V tPLH (1) tPHL (1) VOH Output 50% 50% VOL tPLH(1) tPHL(1) VOH Output 50% 50% VOL A. The maximum between tPLH and TPHL is used for tpd. Figure 7-3. Voltage Waveforms Propagation Delays 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 8 Detailed Description 8.1 Overview This device contains four independent 2-input NAND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B in positive logic. 8.2 Functional Block Diagram One of Four Channels xA xY xB 8.3 Feature Description 8.3.1 Balanced CMOS Push-Pull Outputs A balanced output allows the device to sink and source similar currents. The drive capability of this device may create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to over-current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. 8.3.2 CMOS Schmitt-Trigger Inputs Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, using ohm's law (R = V ÷ I). The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly will also increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers. 8.3.3 Clamp Diode Structure The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 9 SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 VCC Device +IIK +IOK Logic Input Output -IIK -IOK GND Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output 8.4 Device Functional Modes Table 8-1. Function Table INPUTS 10 OUTPUT Y A B H H L L X H X L H Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information In this application, two 2-input NAND gates are used to create an active-low SR latch as shown in Figure 9-1. The two additional gates can be used for a second SR latch, or the inputs can be grounded and both channels left unused. The SN74HCS00 is used to drive the tamper indicator LED and provide one bit of data to the system controller. When the tamper switch outputs LOW, the output Q becomes HIGH. This output remains HIGH until the system controller addresses the event and sends a LOW signal to the R input which returns the Q output back to LOW. The inputs of this active-low SR latch can often be driven by open-drain outputs which can produce slow input transition rates when they transition from LOW to Hi-Z. This makes the SN74HCS00 ideal for the application because it has Schmitt-trigger inputs that do not have input transition rate requirements. 9.2 Typical Application System Controller R1 R Tamper Switch Q S R2 Tamper Indicator Figure 9-1. Typical Application Block Diagram 9.2.1 Design Requirements • • • All signals in the system operate at 5 V Avoid unstable state by not having LOW signals on both inputs Q output is HIGH when S is LOW – Q output remains High until R is LOW 9.2.1.1 Power Considerations Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics. The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN74HCS00 plus the maximum supply current, ICC, listed in the Electrical Characteristics. The logic device can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 11 SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 The SN74HCS00 can drive a load with a total capacitance less than or equal to 50 pF connected to a highimpedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed 50 pF. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. CAUTION The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device. 9.2.1.2 Input Considerations Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do not exceed the maximum input voltage range found in the Absolute Maximum Ratings. Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the SN74HCS00, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ resistor value is often used due to these factors. The SN74HCS00 has no input signal transition rate requirements because it has Schmitt-trigger inputs. Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical Characteristics. This hysteresis value will provide the peak-to-peak limit. Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without causing huge increases in power consumption. The typical additional current caused by holding an input at a value other than VCC or ground is plotted in the Typical Characteristics. Refer to the Feature Description section for additional information regarding the inputs for this device. 9.2.1.3 Output Considerations The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. Similarly, the ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics. Push-pull outputs that could be in the opposite states, even for a very short time period, should never be connected directly together. This can cause excessive current and damage to the device. Two channels within the same device with the same input signals can be connnected in parallel for additional output drive strength. Unused outputs can be left floating. Do no connect outputs directly to VCC or ground. Refer to the Feature Description section for additional information regarding the outputs for this device. 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 9.2.2 Detailed Design Procedure 1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section. 2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; however, it will ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS00 to one or more of the receiving devices. 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in megaohms; much larger than the minimum calculated above. 4. Thermal issues are rarely a concern for logic gates; however, the power consumption and thermal increase can be calculated using the steps provided in the CMOS Power Consumption and Cpd Calculation application report. 9.2.3 Application Curves R S Q Figure 9-2. Application Timing Diagram 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the following layout example. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 13 SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 11 Layout 11.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 11.2 Layout Example GND VCC Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation 0.1 F Avoid 90° corners for signal lines Bypass capacitor placed close to the device 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y Unused inputs tied to VCC Unused output left floating Figure 11-1. Example Layout for the SN74HCS00 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 SN74HCS00 www.ti.com SCLS775C – DECEMBER 2019 – REVISED DECEMBER 2021 12 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: • Texas Instruments, HCMOS Design Considerations application report • Texas Instruments, CMOS Power Consumption and CPD Calculation application report • Texas Instruments, Designing with Logic application report 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS00 15 PACKAGE OPTION ADDENDUM www.ti.com 10-Feb-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74HCS00BQAR ACTIVE WQFN BQA 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCS00 SN74HCS00DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 HCS00 SN74HCS00DYYR ACTIVE SOT-23-THIN DYY 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCS00 SN74HCS00PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 HCS00 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of