SN74HCS273-Q1
SCLS850C – MARCH 2021 – REVISED JANUARY 2023
SN74HCS273-Q1 Automotive Octal D-Type Flip-Flop with Schmitt-Trigger Inputs and
Asynchronous Clear
1 Features
3 Description
•
The SN74HCS273-Q1 device contains eight positiveedge-triggered D-type flip-flops with Schmitt-trigger
inputs, shared asynchronous active low clear (CLR)
input, and shared rising-edge triggered clock (CLK)
input.
•
•
•
•
•
AEC-Q100 Qualified for automotive applications:
– Device temperature grade 1:
–40°C to +125°C, TA
– Device HBM ESD Classification Level 2
– Device CDM ESD Classifcation Level C6
Available in wettable flank QFN (WRKS) package
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input
signals
Low power consumption
– Typical ICC of 100 nA
– Typical input leakage current of ±100 nA
±7.8-mA output drive at 6 V
Package Information
PART NUMBER
SN74HCS273-Q1
(1)
PACKAGE(1)
BODY SIZE (NOM)
PW (TSSOP, 20)
6.50 mm × 4.40 mm
WRKS (VQFN, 20)
4.50 mm × 2.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
Synchronize data to clock
Simple memory – 8 bits
Voltage
Output
Current
Voltage
Current
Output
Input Voltage
Voltage
Output
Time
Current
Response
Waveforms
Voltage
Schmitt-trigger
CMOS Input
Time
Time
Input Voltage
Output
Response
Waveforms
Time
Time
Current
Standard
CMOS Input
Supply Current
Input Voltage
Supports Slow Inputs
Input
Voltage
Noise Rejection
Input
Voltage
Input Voltage
Waveforms
Input
Voltage
Low Power
Supply Current
•
•
Time
Benefits of Schmitt-Trigger Inputs
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HCS273-Q1
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Characteristics.................................................5
6.7 Switching Characteristics............................................6
6.8 Operating Characteristics........................................... 6
6.9 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................11
9 Application and Implementation.................................. 12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
10 Power Supply Recommendations..............................15
11 Layout........................................................................... 15
11.1 Layout Guidelines................................................... 15
11.2 Layout Example...................................................... 15
12 Device and Documentation Support..........................16
12.1 Documentation Support.......................................... 16
12.2 Receiving Notification of Documentation Updates..16
12.3 Support Resources................................................. 16
12.4 Trademarks............................................................. 16
12.5 Electrostatic Discharge Caution..............................16
12.6 Glossary..................................................................16
13 Mechanical, Packaging, and Orderable
Information.................................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2022) to Revision C (January 2023)
Page
• Updated the PW Package 20-Pin TSSOP (Top View) .......................................................................................3
Changes from Revision A (June 2021) to Revision B (February 2022)
Page
• Added WRKS device to Device Information Table..............................................................................................1
• Added WRKS package to pinout image and table..............................................................................................3
• Added WRKS package to specification tables....................................................................................................4
• Added Wettable Flanks topic to Feature Description section............................................................................. 9
• Added WRKS layout diagram........................................................................................................................... 15
Changes from Revision * (March 2021) to Revision A (June 2021)
Page
• Changed from Application Information to Production Data.................................................................................1
2
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5 Pin Configuration and Functions
CLR
1
CLR
20
2
19
8Q
18
8D
1D
3
18
8D
17
7D
2D
4
17
7D
5
16
7Q
2Q
5
16
7Q
6
15
6Q
3Q
6
15
6Q
3D
7
14
6D
4D
8
13
5D
4Q
9
12
5Q
19
1D
3
2D
4
2Q
3Q
14
7
13
8
4Q
12
9
GND
VCC
20
1Q
2
4D
1
8Q
1Q
3D
VCC
11
10
PAD
6D
5D
5Q
CLK
10
GND
PW Package
20-Pin TSSOP
(Top View)
11
CLK
WRKS Package
20-Pin VQFN
(Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
CLR
1
Input
1Q
2
Output
1D
3
Input
Input for channel 1
2D
4
Input
Input for channel 2
2Q
5
Output
Output for channel 2
3Q
6
Output
Output for channel 3
3D
7
Input
Input for channel 3
4D
8
Input
Input for channel 4
4Q
9
Output
GND
10
—
CLK
11
Input
5Q
12
Output
5D
13
Input
Input for channel 5
6D
14
Input
Input for channel 6
6Q
15
Output
Output for channel 6
7Q
16
Output
Output for channel 7
7D
17
Input
Input for channel 7
8D
18
Input
Input for channel 8
8Q
19
Output
VCC
20
—
Postive supply
—
The thermal pad can be connect to GND or left floating. Do not connect to any other signal
or supply.
Thermal Pad(1)
(1)
Clear for all channels, active low
Output for channel 1
Output for channel 4
Ground
Clock for all channels, rising edge triggered
Output for channel 5
Output for channel 8
WRKS package only.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VCC
Supply voltage
IIK
Input clamp current(2)
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
ICC
Continuous current through VCC or GND
±70
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–0.5
UNIT
7
–65
V
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC
HBM ESD Classification Level 2
Q100-002(1)
UNIT
±4000
V
Charged device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
±1500
AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
6
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
TA
Ambient temperature
–40
125
°C
6.4 Thermal Information
SN74HCS273-Q1
THERMAL METRIC(1)
PW (TSSOP)
UNIT
20 PINS
20 PINS
RθJA
Junction-to-ambient thermal resistance
83.2
134.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
82.6
74.6
°C/W
RθJB
Junction-to-board thermal resistance
57.4
86
°C/W
ΨJT
Junction-to-top characterization parameter
14.5
22.5
°C/W
ΨJB
Junction-to-board characterization parameter
56.4
85.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
40.0
N/A
°C/W
(1)
4
WRKS (VQFN)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
VT+
VT-
ΔVT
VOH
VOL
TEST CONDITIONS
VCC
Positive switching threshold
Negative switching threshold
Hysteresis (VT+ - VT-)
High-level output voltage
Low-level output voltage
VI = VIH or VIL
VI = VIH or VIL
MIN
TYP
MAX UNIT
2V
0.7
1.5
4.5 V
1.7
3.15
6V
2.1
4.2
2V
0.3
1
4.5 V
0.9
2.2
6V
1.2
3
2V
0.2
1
4.5 V
0.4
1.4
6V
0.6
1.6
IOH = -20 µA
2 V to 6 V
IOH = -6 mA
4.5 V
VCC – 0.1
VCC – 0.002
4
4.3
IOH = -7.8 mA
6V
IOL = 20 µA
2 V to 6 V
IOL = 6 mA
4.5 V
0.18
0.3
IOL = 7.8 mA
6V
0.22
0.33
5.4
V
V
V
V
5.75
0.002
0.1
V
II
Input leakage current
VI = VCC or 0
6V
±100
±1000
nA
ICC
Supply current
VI = VCC or 0, IO = 0
6V
0.1
2
µA
Ci
Input capacitance
5
pF
2 V to 6 V
6.6 Timing Characteristics
over operating free-air temperature range (unless otherwise noted), CL = 50 pF
PARAMETER
CONDITION
VCC
MIN
2V
fclock
Clock Frequency
120
6V
135
tw
Pulse duration
CLK high or low
Data before CLK↑
tsu
Setup time
CLR inactive
th
Hold time, data after CLK↑
4.5 V
MHz
12
6
6V
6
2V
12
4.5 V
6
6V
6
2V
18
4.5 V
UNIT
49
4.5 V
2V
CLR low
MAX
6
6V
6
2V
18
4.5 V
6
6V
6
2V
0
4.5 V
0
6V
0
ns
ns
ns
ns
ns
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6.7 Switching Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter
Measurment Information. CL = 50 pF.
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
MIN
2V
fmax
tdis
tpd
tt
Max frequency
Disable time
CLR
Propagation delay
Any Q
CLK
Any Q
Transition-time
Any Q
TYP
MAX
UNIT
49
4.5 V
120
6V
135
MHz
2V
27.3
31.2
4.5 V
13.3
14.8
6V
11.7
13.2
2V
29.1
34.6
4.5 V
13.9
16.4
6V
12.1
14.3
2V
14.6
19.4
4.5 V
7.7
9.6
6V
7.4
10.4
ns
ns
ns
6.8 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
Cpd
6
TEST CONDITIONS
Power dissipation capacitance per gate
No load
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MIN
TYP
20
MAX
UNIT
pF
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6.9 Typical Characteristics
TA = 25°C
70
46
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
Output Resistance (:)
42
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
65
Output Resistance (:)
44
40
38
36
34
32
60
55
50
45
40
30
35
28
26
30
0
2.5
5
7.5 10 12.5 15 17.5
Output Sink Current (mA)
20
22.5
25
Figure 6-1. Output Driver Resistance in LOW State
0
ICC ± Supply Current (mA)
VCC = 2.5 V
0.14
VCC = 3.3 V
ICC ± Supply Current (mA)
VCC = 2 V
0.16
0.12
0.1
0.08
0.06
0.04
0.02
0
0
0.5
1
1.5
2
2.5
VI ± Input Voltage (V)
3
3.5
Figure 6-3. Supply Current Across Input Voltage,
2-, 2.5-, and 3.3-V Supply
5
7.5 10 12.5 15 17.5
Output Source Current (mA)
20
22.5
25
Figure 6-2. Output Driver Resistance in HIGH State
0.2
0.18
2.5
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
0
0.5
1
1.5
2 2.5 3 3.5 4
VI ± Input Voltage (V)
4.5
5
5.5
6
Figure 6-4. Supply Current Across Input Voltage,
4.5-, 5-, and 6-V Supply
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
tw
Test
Point
VCC
Input
From Output
Under Test
50%
50%
0V
Figure 7-2. Voltage Waveforms, Pulse Duration
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 7-1. Load Circuit for Push-Pull Outputs
VCC
VCC
Clock
Input
Input
50%
50%
50%
0V
0V
tsu
tPLH
th
(1)
tPHL
(1)
VOH
VCC
Data
Input
50%
Output
50%
50%
50%
VOL
0V
Figure 7-3. Voltage Waveforms, Setup and Hold
Times
tPLH(1)
tPHL(1)
VOH
Output
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-4. Voltage Waveforms Propagation Delays
90%
VCC
90%
Input
10%
10%
tr(1)
0V
tf(1)
90%
VOH
90%
Output
10%
10%
tr(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 7-5. Voltage Waveforms, Input and Output Transition Times
8
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8 Detailed Description
8.1 Overview
The SN74HCS273-Q1 contains 8 positive-edge-triggered D-type flip-flops with shared direct active low clear
(CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the (Q) outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level or
transitioning from a high level to a low level, the D input has no effect at the output.
Information at the data (Q) outputs can be asychronously cleared with a low level input through the clear (CLR)
pin.
8.2 Functional Block Diagram
Shared Control Inputs
CLK
C
C
CLR
R
One One
of Eight
D-Type
Flip-Flops
of Eight
Channels
C
xQ
C
C
xD
C
C
C
C
C
R
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads, so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.2 CMOS Schmitt-Trigger Inputs
This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are
typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table
from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the
Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics
table, using Ohm's law (R = V ÷ I).
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The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics
table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional
information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
8.3.3 Clamp Diode Structure
As shown in Figure 8-1, the inputs and outputs to this device have both positive and negative clamping diodes.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
Device
VCC
+IIK
+IOK
Logic
Input
-IIK
Output
-IOK
GND
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Wettable Flanks
This device includes wettable flanks for at least one package. See the Features section on the front page of the
data sheet for which packages include this feature.
Package
Weable Flank Lead
Package
Solder
Standard Lead
Pad
PCB
Figure 8-2. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After
Soldering
Wettable flanks help improve side wetting after soldering, which makes QFN packages easier to inspect with
automatic optical inspection (AOI). As shown in Figure 8-2, a wettable flank can be dimpled or step-cut to
provide additional surface area for solder adhesion which assists in reliably creating a side fillet. See the
mechanical drawing for additional details.
10
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8.4 Device Functional Modes
Table 8-1. Function Table
INPUTS(1)
(1)
(2)
OUTPUT(2)
CLR
CLK
D
Q
L
X
X
L
H
L, H, ↓
X
Q0
H
↑
L
L
H
↑
H
H
L = input low, H = input high, ↑ = input transitioning from low to
high, ↓ = input transitioning from high to low, X = do not care
L = output low, H = output high, Q0 = previous state
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, the SN74HCS273-Q1 is used to synchronize incoming data to the system clock on an 8-bit
bus.
9.2 Typical Application
1Q
2D
2Q
3D
3Q
D-Type Flip-Flops
1D
4D
5D
6D
7D
4Q
5Q
6Q
7Q
CLK
8Q
CLR
8D
Input Data Bus
Output Data Bus
CLK
Bus Controller
CLR
Figure 9-1. Typical Application Diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced
by all outputs of the SN74HCS273-Q1 plus the maximum static supply current, ICC, listed in the Electrical
Characteristics, and any transient current required for switching. The logic device can only source as much
current that is provided by the positive supply source. Be sure to not exceed the maximum total current through
VCC listed in the Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HCS273-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any
transient current required for switching. The logic device can only sink as much current that can be sunk into
its ground connection. Be sure to not exceed the maximum total current through GND listed in the Absolute
Maximum Ratings.
The SN74HCS273-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting
all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to
exceed 50 pF.
12
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The SN74HCS273-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state,
the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SN74HCS273-Q1 (as
specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS273-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
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9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; it will, however, ensure
optimal performance. This can be accomplished by providing short, appropriately sized traces from the
SN74HCS273-Q1 to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curve
CLR
CLK
D1
Q1
Figure 9-2. Application Timing Diagram, One Data Channel Shown
14
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the
following layout example.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases,
functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
GND VCC
0.1 F
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placed close to the
device
F
CLR
VCC
1Q
2
1
20
19
8Q
1D
3
18
8D
4
17
7D
16
7Q
15
6Q
7
14
6D
4D
8
13
5D
4Q
9
10
12
11
5Q
CLR
1Q
1
20
VCC
2
19
8Q
1D
3
18
2D
4
17
2Q
5
16
8D Unused input
7D tied to GND
7Q
3Q
3D
6
15
6Q
3Q
6
7
8
9
10
14
13
12
11
6D
3D
4D
4Q
GND
Unused output
left floating
Unused input
tied to GND 2D
Unused output 2Q
left floating
5D
5Q
CLK
Avoid 90°
corners for
signal lines
Avoid 90°
corners for
signal lines
Figure 11-1. Example Layout for the SN74HCS273Q1 PW Package
GND
5
GND
GND
Bypass capacitor
placed close to the
device
CLK
Figure 11-2. Example Layout for the SN74HCS273Q1 WRKS Package
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
•
•
Texas Instruments, HCMOS Design Considerations application report
Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
Texas Instruments, Designing With Logic application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
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9-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74HCS273QPWRQ1
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCS273Q
Samples
SN74HCS273QWRKSRQ1
ACTIVE
VQFN
RKS
20
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCS273Q
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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