SN74HCS367QPWRQ1

SN74HCS367-Q1 SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 SN74HCS367-Q1 Automotive Hex Buffers and Line Drivers With Schmitt-Trigger Inputs and 3-State Outputs 1 Features 3 Description • The SN74HCS367-Q1 is a hex buffer with 3-state outputs and Schmitt-trigger inputs. The device is configured into two banks, one with four drivers and one with two drivers, each controlled by its own output enable pin. SN74HCS367PW-Q1 TSSOP (16) 5.00 mm × 4.40 mm SN74HCS367D-Q1 SOIC (16) 9.90 mm × 3.90 mm SN74HCS367WBQB-Q1 WQFN (16) (1) 2 Applications 3.60 mm × 2.60 mm For all available packages, see the orderable addendum at the end of the data sheet. Enable or Disable a Digital Signal Eliminate Slow or Noisy Input Signals Hold a Signal During Controller Reset Debounce a Switch Response Waveforms Voltage Output Current Voltage Current Output Input Voltage Voltage Schmitt-trigger CMOS Input Time Time Input Voltage Output Response Waveforms Time Time Current Standard CMOS Input Supply Current Input Voltage Supports Slow Inputs Input Voltage Noise Rejection Input Voltage Input Voltage Waveforms Input Voltage Low Power Supply Current • • • • BODY SIZE (NOM) Time Voltage • PACKAGE(1) Output • Device Information PART NUMBER Current • • • AEC-Q100 qualified for automotive applications: – Device temperature grade 1: –40°C to +125°C, TA – Device HBM ESD Classification Level 2 – Device CDM ESD Classifcation Level C6 Available in wettable flank QFN (WBQB) package Wide operating voltage range: 2 V to 6 V Schmitt-trigger inputs allow for slow or noisy input signals Low power consumption – Typical ICC of 100 nA – Typical input leakage current of ±100 nA ±7.8-mA output drive at 6 V Time Benefits of Schmitt-trigger inputs An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................4 6.5 Electrical Characteristics.............................................6 6.6 Switching Characteristics............................................6 6.7 Operating Characteristics........................................... 7 6.8 Typical Characteristics................................................ 7 7 Parameter Measurement Information............................ 8 8 Detailed Description........................................................9 8.1 Overview..................................................................... 9 8.2 Functional Block Diagram........................................... 9 8.3 Feature Description.....................................................9 8.4 Device Functional Modes..........................................11 9 Application and Implementation.................................. 12 9.1 Application Information............................................. 12 9.2 Typical Application.................................................... 12 10 Power Supply Recommendations..............................15 11 Layout........................................................................... 15 11.1 Layout Guidelines................................................... 15 11.2 Layout Example...................................................... 15 12 Device and Documentation Support..........................16 12.1 Documentation Support.......................................... 16 12.2 Receiving Notification of Documentation Updates..16 12.3 Support Resources................................................. 16 12.4 Trademarks............................................................. 16 12.5 Electrostatic Discharge Caution..............................16 12.6 Glossary..................................................................16 13 Mechanical, Packaging, and Orderable Information.................................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (September 2020) to Revision A (December 2021) Page • Added WBQB package information to Device Information................................................................................. 1 • Added WBQB package to Pin Configuration and Functions ..............................................................................3 • Added WBQB package to Thermal Information table.........................................................................................4 • Added Wettable Flanks section to Feature Description .....................................................................................9 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 5 Pin Configuration and Functions 1OE VCC 1OE 1A1 1 16 VCC 2 2OE 1A1 2 15 2OE 1Y1 3 15 14 2A2 1Y1 3 2A2 1A2 4 13 2Y2 1A2 4 14 13 1Y2 5 12 2A1 1Y2 5 12 1A3 6 11 6 11 2Y1 7 8 10 2Y1 1A4 1Y4 1A3 1Y3 GND 1Y3 7 10 1A4 9 1 16 PAD 8 2Y2 2A1 9 GND 1Y4 D or PW Package 20-Pin SOIC or TSSOP Top View WBQB Package 20-Pin WQFN Top View Pin Functions PIN SOIC or TSSOP NO. (1) NAME I/O DESCRIPTION 1 1OE I Bank 1, output enable, active low 2 1A1 I Bank 1, channel 1 input 3 1Y1 O Bank 1, channel 1 output 4 1A2 I Bank 1, channel 2 input 5 1Y2 O Bank 1, channel 2 output 6 1A3 I Bank 1, channel 3 input 7 1Y3 O Bank 1, channel 3 output 8 GND — Ground 9 1Y4 O Bank 1, channel 4 output 10 1A4 I Bank 1, channel 4 input 11 2Y1 O Bank 2, channel 1 output 12 2A1 I Bank 2, channel 1 input 13 2Y2 O Bank 2, channel 2 output 14 2A2 I Bank 2, channel 2 input 15 2OE I Bank 2, output enable, active low 16 VCC — Positive supply — The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply. Thermal Pad(2) (1) (2) Signal Types: I = Input, O = Output, I/O = Input or Output. WBQB package only. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 3 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX –0.5 UNIT VCC Supply voltage IIK Input clamp current(2) VI < –0.5 V or VI > VCC + 0.5 V ±20 7 mA V IOK Output clamp current(2) VI < –0.5 V or VI > VCC + 0.5 V ±20 mA IO Continuous output current VO = 0 to VCC ±35 mA Continuous current through VCC or GND ±70 mA TJ Junction temperature(3) 150 °C Tstg Storage temperature 150 °C (1) (2) (3) –65 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Guaranteed by design. 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) HBM ESD Classification Level 2 ±4000 Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C6 ±1500 UNIT V AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX VCC Supply voltage 2 5 6 UNIT V VI Input voltage 0 VCC V VO Output voltage 0 VCC V TA Ambient temperature –40 125 °C 6.4 Thermal Information SN74HCS367-Q1 THERMAL 4 METRIC(1) PW (TSSOP) D (SOIC) WBQB (WQFN) 16 PINS 16 PINS 16 PINS UNIT RθJA Junction-to-ambient thermal resistance 141.2 122.2 97.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 78.8 80.9 93.8 °C/W RθJB Junction-to-board thermal resistance 85.8 80.6 66.4 °C/W ΨJT Junction-to-top characterization parameter 27.7 40.4 14.6 °C/W ΨJB Junction-to-board characterization parameter 85.5 80.3 66.4 °C/W Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 SN74HCS367-Q1 THERMAL METRIC(1) RθJC(bot) (1) Junction-to-case (bottom) thermal resistance PW (TSSOP) D (SOIC) WBQB (WQFN) 16 PINS 16 PINS 16 PINS N/A N/A 44.3 UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 5 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 6.5 Electrical Characteristics over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER VT+ VT- ΔVT VOH VOL TEST CONDITIONS VCC Positive switching threshold Negative switching threshold Hysteresis (VT+ - VT- )(1) High-level output voltage Low-level output voltage VI = VIH or VIL VI = VIH or VIL MIN TYP MAX UNIT 2V 0.7 1.5 4.5 V 1.7 3.15 6V 2.1 4.2 2V 0.3 1.0 4.5 V 0.9 2.2 6V 1.2 3.0 2V 0.2 1.0 4.5 V 0.4 1.4 6V 0.6 1.6 IOH = -20 µA 2 V to 6 V VCC – 0.1 VCC – 0.002 IOH = -6 mA 4.5 V 4.0 4.3 IOH = -7.8 mA 6V 5.4 IOL = 20 µA 2 V to 6 V IOL = 6 mA IOL = 7.8 mA V V V V 5.75 0.002 0.1 4.5 V 0.18 0.30 6V 0.22 0.33 ±0.1 ±1 µA ±0.5 µA 2 µA 5 pF II Input leakage current VI = VCC or 0 6V IOZ Off-state (high-impedance state) output current VO = VCC or 0 6V ICC Supply current VI = VCC or 0, IO = 0 6V Ci Input capacitance (1) Guaranteed by design. 0.1 2 V to 6 V V 6.6 Switching Characteristics CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information. Operating free-air temperature (TA) PARAMETER FROM TO VCC 25°C MIN ten tdis Propagation delay Enable time Disable time A OE OE Y Y MAX 14 21 32 4.5 V 6 10 15 6V 5 9 12 2V 14 21 36 7 12 15 Y 4.5 V Transition-time MAX 6 9 13 2V 13 21 24 4.5 V 9 13 16 6V 8 12 15 9 16 5 9 4 8 Any output 4.5 V 6V 6 TYP 6V 2V tt MIN UNIT TYP 2V tpd –40°C to 125°C Submit Document Feedback ns ns ns ns Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 6.7 Operating Characteristics over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS Power dissipation capacitance No load per gate Cpd VCC MIN 2 V to 6 V TYP MAX UNIT 15 pF 6.8 Typical Characteristics TA = 25°C 70 46 VCC = 2 V VCC = 3.3 V VCC = 4.5 V VCC = 6 V Output Resistance (:) 42 VCC = 2 V VCC = 3.3 V VCC = 4.5 V VCC = 6 V 65 Output Resistance (:) 44 40 38 36 34 32 60 55 50 45 40 30 35 28 26 30 0 2.5 5 7.5 10 12.5 15 17.5 Output Sink Current (mA) 20 22.5 25 0 2.5 5 7.5 10 12.5 15 17.5 Output Source Current (mA) 20 22.5 25 Figure 6-1. Output Driver Resistance in LOW State Figure 6-2. Output Driver Resistance in HIGH State. 0.2 ICC ± Supply Current (mA) 0.16 VCC = 2.5 V 0.14 VCC = 3.3 V ICC ± Supply Current (mA) VCC = 2 V 0.18 0.12 0.1 0.08 0.06 0.04 0.02 0 0 0.5 1 1.5 2 2.5 VI ± Input Voltage (V) 3 3.5 Figure 6-3. Supply Current Across Input Voltage, 2-, 2.5-, and 3.3-V Supply 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 VCC = 4.5 V VCC = 5 V VCC = 6 V 0 0.5 1 1.5 2 2.5 3 3.5 4 VI ± Input Voltage (V) 4.5 5 5.5 6 Figure 6-4. Supply Current Across Input Voltage, 4.5-, 5-, and 6-V Supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 7 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 7 Parameter Measurement Information Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. VCC Test Point VCC Input 50% 50% S1 0V RL From Output Under Test CL(1) tPHL(1) tPLH(1) VOH S2 Output 50% 50% VOL (1) CL includes probe and test-fixture capacitance. tPLH(1) tPHL(1) Figure 7-1. Load Circuit for 3-State Outputs VOH Output 50% 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. Figure 7-2. Voltage Waveforms Propagation Delays VCC Output Control 50% 90% tPZL Output Waveform 1 S1 at VLOAD(1) tr(1) (4) § 9CC 90% 10% VOH 90% 10% VOL (3) 0V tf(1) Output 50% tPZH Output Waveform 2 S1 at GND(2) tPLZ 10% 10% 0V (3) VCC 90% Input 50% tPHZ (4) 90% VOH 50% 10% tr(1) tf(1) VOL (1) The greater between tr and tf is the same as tt. Figure 7-4. Voltage Waveforms, Input and Output Transition Times §0V Figure 7-3. Voltage Waveforms Propagation Delays 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 8 Detailed Description 8.1 Overview The SN74HCS367-Q1 contains 6 individual high speed CMOS buffers with Schmitt-trigger inputs and 3-state outputs. Each buffer performs the boolean logic function xYn = xAn, with x being the bank number and n being the channel number. The first bank includes four buffers, and the second bank includes two buffers. Each output enable (xOE) controls one bank of buffers. When the xOE pin is in the low state, the outputs of all buffers in the bank x are enabled. When the xOE pin is in the high state, the outputs of all buffers in the bank x are disabled. All disabled output are placed into the high-impedance state. To ensure the high-impedance state during power up or power down, both xOE pins should be tied to VCC through a pull-up resistor. The value of the resistor is determined by the current sinking capability of the driver and the leakage of the pin as defined in the Electrical Characteristics table. Typically a 10 kΩ resistor will be sufficient. 8.2 Functional Block Diagram 1OE 1A1 1Y1 1A2 1Y2 1A3 1Y3 1A4 1Y4 2OE 2A1 2Y1 2A2 2Y2 Figure 8-1. Logic Diagram (Positive Logic) for SN74HCS367-Q1 8.3 Feature Description 8.3.1 Balanced CMOS 3-State Outputs This device includes balanced CMOS 3-State outputs. The three states that these outputs can be in are driving high, driving low, and high impedance. The term "balanced" indicates that the device can sink and source similar currents. The drive capability of this device may create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 9 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 can be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption limitations. Typically, a 10 kΩ resistor can be used to meet these requirements. Unused 3-state CMOS outputs should be left disconnected. 8.3.2 CMOS Schmitt-Trigger Inputs This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics table, using Ohm's law (R = V ÷ I). The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers. 8.3.3 Clamp Diode Structure The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical Placement of Clamping Diodes for Each Input and Output. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed. Device VCC +IIK +IOK Logic Input -IIK Output -IOK GND Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output 8.3.4 Wettable Flanks This device includes wettable flanks for at least one package. See the Features section on the front page of the data sheet for which packages include this feature. 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 Package Package Solder We
able Flank Lead Standard Lead Pad PCB Figure 8-3. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After Soldering Wettable flanks help improve side wetting after soldering which makes QFN packages easier to inspect with automatic optical inspection (AOI). A wettable flank can be dimpled or step-cut to provide additional surface area for solder adhesion which assists in reliably creating a side fillet as shown in Figure 8-3. Please see the mechanical drawing for additional details. 8.4 Device Functional Modes Function Table lists the functional modes of the SN74HCS367-Q1. Table 8-1. Function Table INPUTS(1) (2) xOE (1) (2) OUTPUTS(1) (2) xAn xYn L L L L H H H X Z H = High Voltage Level, L = Low Voltage Level, X = Don't Care, Z = High-Impedance State x = bank number, n = channel number Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 11 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN74HCS367-Q1 can be used to drive signals over relatively long traces or transmission lines. In order to reduce ringing caused by impedance mismatches between the driver, transmission line, and receiver, a series damping resistor placed in series with the transmitter’s output can be used. The plot in the Application Curve section shows the received signal with three separate resistor values. Just a small amount of resistance can make a significant impact on signal integrity in this type of application. 9.2 Typical Application Rd System Controller Z0 Peripheral L > 12 cm Transmitter Receiver Figure 9-1. Typical application block diagram 9.2.1 Design Requirements 9.2.1.1 Power Considerations Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics. The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN74HCS367-Q1 plus the maximum static supply current, ICC, listed in Electrical Characteristics and any transient current required for switching. The logic device can only source as much current as is provided by the positive supply source. Be sure not to exceed the maximum total current through VCC listed in the Absolute Maximum Ratings. The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the SN74HCS367-Q1 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient current required for switching. The logic device can only sink as much current as can be sunk into its ground connection. Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum Ratings. The SN74HCS367-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed 50 pF. The SN74HCS367-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state, the output voltage in the equation is defined as the difference between the measured output voltage and the supply voltage at the VCC pin. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 CAUTION The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device. 9.2.1.2 Input Considerations Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do not exceed the maximum input voltage range found in the Absolute Maximum Ratings. Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the SN74HCS367-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ resistor value is often used due to these factors. The SN74HCS367-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs. Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical Characteristics. This hysteresis value will provide the peak-to-peak limit. Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without causing huge increases in power consumption. The typical additional current caused by holding an input at a value other than VCC or ground is plotted in the Typical Characteristics. Refer to the Feature Description section for additional information regarding the inputs for this device. 9.2.1.3 Output Considerations The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics. Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected directly together. This can cause excessive current and damage to the device. Two channels within the same device with the same input signals can be connected in parallel for additional output drive strength. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to Feature Description section for additional information regarding the outputs for this device. 9.2.2 Detailed Design Procedure 1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section. 2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS367-Q1 to the receiving device(s). 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in megaohms; much larger than the minimum calculated above. 4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 13 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 9.2.3 Application Curve 5 0 22 50 4 3.3 2 1 0 -1 -2 0 15 30 45 60 Time (ns) 75 90 100 Figure 9-2. Simulated signal integrity at the reciever with different damping resistor (Rd) values 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in given example layout image. 11 Layout 11.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 11.2 Layout Example GND VCC Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation 0.1 F Avoid 90° corners for signal lines 1OE 1 1A1 2 1Y1 Bypass capacitor placed close to the device 16 VCC 15 2OE 3 14 2A2 close to output 1A2 4 13 2Y2 1Y2 5 12 2A1 1A3 1Y3 GND 6 11 2Y1 7 8 10 9 1A4 1Y4 Unused input tied to GND Damping resistor placed 33 33 Unused output left floating Figure 11-1. Example layout for the SN74HCS367-Q1 in the PW package. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 15 SN74HCS367-Q1 www.ti.com SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 12 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • • • Texas Instruments, HCMOS Design Considerations application report (SCLA007) Texas Instruments, CMOS Power Consumption and Cpd Calculation application report (SDYA009) Texas Instruments, Designing With Logic application report 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary 16 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 www.ti.com SN74HCS367-Q1 SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 17 PACKAGE OPTION ADDENDUM www.ti.com 19-Dec-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74HCS367QDRQ1 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCS367Q SN74HCS367QPWRQ1 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCS367Q SN74HCS367QWBQBRQ1 ACTIVE WQFN BQB 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CS367Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of