SN74HCT00DR

SN54HCT00, SN74HCT00 ZHCSPU0F – NOVEMBER 1988 – REVISED OCTOBER 2022 SNx4HCT00 四路 2 输入正与非门 1 特性 • • • • • • • 2 说明 4.5V 至 5.5V 的工作电压范围 输出可驱动多达 10 个 LSTTL 负载 低功耗，ICC 最大值为 20μA 典型值 tpd = 10ns ±4mA 输出驱动（在 5V 时） 低输入电流，最大值 1μA 输入兼容 TTL 电压 这些器件包含四个独立的 2 输入与非门。它们以正逻 辑执行布尔函数 Y= A • B。 (1) 器件信息 器件型号 封装 封装尺寸（标称值） SN74HCT00D SOIC (14) 8.65mm × 3.90mm SN74HCT00DBR SSOP (14) 6.20mm × 5.30mm SN74HCT00N PDIP (14) 19.31mm × 6.35mm SN74HCT00NSR SO (14) 10.20mm × 5.30mm SN74HCT00PW TSSOP (14) 5.00mm × 4.40mm (1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附 录。 xA xY xB 功能方框图 本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。 English Data Sheet: SCLS062 SN54HCT00, SN74HCT00 www.ti.com.cn ZHCSPU0F – NOVEMBER 1988 – REVISED OCTOBER 2022 Table of Contents 1 特性................................................................................... 1 2 说明................................................................................... 1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 (1) 5.2 Recommended Operating Conditions ..................... 4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Switching Characteristics ...........................................5 5.6 Operating Characteristics........................................... 5 6 Parameter Measurement Information............................ 6 7 Detailed Description........................................................7 7.1 Overview..................................................................... 7 7.2 Functional Block Diagram........................................... 7 7.3 Device Functional Modes............................................7 8 Power Supply Recommendations..................................8 9 Layout...............................................................................8 9.1 Layout Guidelines....................................................... 8 10 Device and Documentation Support............................9 10.1 Documentation Support............................................ 9 10.2 接收文档更新通知..................................................... 9 10.3 支持资源....................................................................9 10.4 Trademarks............................................................... 9 10.5 Electrostatic Discharge Caution................................9 10.6 术语表....................................................................... 9 11 Mechanical, Packaging, and Orderable Information...................................................................... 9 3 Revision History 注：以前版本的页码可能与当前版本的页码不同 Changes from Revision E (February 2022) to Revision F (October 2022) Page • Increased RθJA for packages: D (86 to 138.7); DB (96 to 117.9); N (80 to 69.5); NS (76 to 95.3); PW (113 to 122.8)..................................................................................................................................................................4 Changes from Revision D (August 2003) to Revision E (February 2022) Page • 更新了整个文档中的编号、格式、表格、图和交叉参考，以反映现代数据表标准.............................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT00 SN74HCT00 SN54HCT00, SN74HCT00 www.ti.com.cn ZHCSPU0F – NOVEMBER 1988 – REVISED OCTOBER 2022 4 Pin Configuration and Functions D, DB, N, NS, PW, J or W Package 14-Pin SOIC, SSOP, PDIP, SO, TSSOP Top View FK Package 20-Pin LCCC Top View Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT00 SN74HCT00 3 SN54HCT00, SN74HCT00 www.ti.com.cn ZHCSPU0F – NOVEMBER 1988 – REVISED OCTOBER 2022 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC Supply voltage range (2) IIK Input clamp current IOK Output clamp current IO Continuous output current VCC or GND Continuous current through TJ Junction temperature Tstg Storage temperature (1) (2) (2) MIN MAX -0.5 7 UNIT V (VI < 0 or VI > VCC) ±20 mA (VO < 0 or VO > VCC) ±20 mA (VO = 0 to VCC) ±25 mA ±50 mA 150 °C 150 °C -65 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. (1) 5.2 Recommended Operating Conditions SN54HCT00(2) SN74HCT00 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC Supply voltage VIH High-level input voltage VCC = 4.5 V to 5.5 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V Δt/Δv Input transition rise/fall time 500 ns TA Operating free-air temperature 85 °C (1) (2) 2 V 0.8 500 – 55 V 2 125 – 40 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report Implications of Slow or Floating SMOS Inputs, literature number SCBA004. SN54HCT00 is in product preview. 5.3 Thermal Information THERMAL METRIC DB (SSOP) N (PDIP) NS (SO) PW (TSSOP) 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal (1) resistance 138.7 117.9 69.5 95.3 122.8 °C/W RθJC (top) Junction-to-case (top) thermal resistance 93.8 63.1 57.6 52.9 52.1 °C/W RθJB Junction-to-board thermal resistance 94.7 66.9 49.3 55.9 65.8 °C/W ΨJT Junction-to-top characterization parameter 49.1 22.2 37.6 19.5 7.8 °C/W ΨJB Junction-to-board characterization parameter 94.3 66.2 49.1 55.4 65.3 °C/W RθJC (bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A N/A °C/W (1) 4 D (SOIC) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT00 SN74HCT00 SN54HCT00, SN74HCT00 www.ti.com.cn ZHCSPU0F – NOVEMBER 1988 – REVISED OCTOBER 2022 5.4 Electrical Characteristics PARAMETER TEST CONDITIONS(1) IOH = –20 μA VOH High-level output voltage VOL Low-level output voltage II Input hold current VI = VCC or 0 5.5 ICC Supply current VI = VCC or 0. IO = 0 5.5 (2) Supply-current change One input at 0.5V or 2.4 V, Other inputs at 0 or VCC Ci Input capacitance ΔICC (1) (2) (3) 4.5 IOH = –4 mA IOL = 20 μA 5.5 IOL = 4 mA SN54HCT00(3) TA = 25°C VCC (V) MAX MIN MAX SN74HCT00 MIN TYP MIN 4.4 4.499 4.4 4.4 3.98 4.3 3.7 3.84 MAX UNIT V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 ±0.1 ±100 ±1000 ±1000 nA 2 40 20 μA 2.9 mA 10 pF V 3 5.5 4.5 to 5.5 1.4 2.4 3 10 10 VI = VIH or VIL, unless otherwise noted. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. SN54HCT00 is in product preview. 5.5 Switching Characteristics CL = 50 pF. See Parameter Measurement Information PARAMETER tpd Propagation delay tt Transition time (1) FROM (INPUT) TO (OUTPUT) A or B Y Y VCC (V) SN54HCT00(1) TA = 25°C MIN MIN MAX SN74HCT00 TYP MAX MIN MAX 4.5 11 20 30 25 5.5 10 18 27 22 4.5 9 15 22 19 5.5 8 14 20 17 ns ns SN54HCT00 is in product preview. 5.6 Operating Characteristics TA = 25°C Cpd Power dissipation capacitance Test Conditions TYP UNIT No load 20 pF Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT00 SN74HCT00 5 SN54HCT00, SN74HCT00 www.ti.com.cn ZHCSPU0F – NOVEMBER 1988 – REVISED OCTOBER 2022 6 Parameter Measurement Information Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. Test Point From Output Under Test CL(1) (1) CL includes probe and test-fixture capacitance. 图 6-1. Load Circuit for Push-Pull Outputs 3V Input 1.3V 1.3V 0V tPLH(1) tPHL(1) VOH Output Waveform 1 50% 50% VOL tPLH(1) tPHL(1) VOH Output Waveform 2 50% 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. 图 6-2. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT00 SN74HCT00 SN54HCT00, SN74HCT00 www.ti.com.cn ZHCSPU0F – NOVEMBER 1988 – REVISED OCTOBER 2022 7 Detailed Description 7.1 Overview These devices contain four independent 2-input NAND gates. They perform the Boolean function Y = A • B in positive logic. 7.2 Functional Block Diagram xA xY xB 7.3 Device Functional Modes 表 7-1. Function Table (each gate) Inputs Output A B Y H H L L X H X L H Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT00 SN74HCT00 7 SN54HCT00, SN74HCT00 ZHCSPU0F – NOVEMBER 1988 – REVISED OCTOBER 2022 www.ti.com.cn 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT00 SN74HCT00 SN54HCT00, SN74HCT00 www.ti.com.cn ZHCSPU0F – NOVEMBER 1988 – REVISED OCTOBER 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Documentation Support 10.1.1 Related Documentation 10.2 接收文档更新通知 要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更 改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。 10.3 支持资源 TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解 答或提出自己的问题可获得所需的快速设计帮助。 链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。 10.4 Trademarks TI E2E™ is a trademark of Texas Instruments. 所有商标均为其各自所有者的财产。 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 术语表 TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT00 SN74HCT00 9 PACKAGE OPTION ADDENDUM www.ti.com 24-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74HCT00D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT00 Samples SN74HCT00DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT00 Samples SN74HCT00DE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT00 Samples SN74HCT00DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT00 Samples SN74HCT00DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HCT00 Samples SN74HCT00DRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT00 Samples SN74HCT00DT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT00 Samples SN74HCT00N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HCT00N Samples SN74HCT00NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT00 Samples SN74HCT00PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT00 Samples SN74HCT00PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HT00 Samples SN74HCT00PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT00 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of