SN54HCT08, SN74HCT08
SCLS063F – NOVEMBER 1988 – REVISED OCTOBER 2022
SNx4HCT08 Quadruple 2-Input Positive-AND Gates
1 Features
2 Description
•
•
•
•
•
•
•
These devices contain four independent 2-input AND
gates. They perform the Boolean function Y = A • B in
positive logic.
Operating voltage range of 4.5 V to 5.5 V
Outputs can drive up to 10 LSTTL loads
Low power consumption, 20-µA max ICC
Typical tpd = 13 ns
±4-mA output drive at 5 V
Low input current of 1 µA max
Inputs are TTL-Voltage compatible
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HCT08D
SOIC (14)
8.65 mm × 3.90 mm
SN74HCT08DB
SSOP (14)
6.20 mm × 5.30 mm
SN74HCT08N
PDIP (14)
19.31 mm × 6.35 mm
SN74HCT08NS
SO (14)
10.20 mm × 5.30 mm
SN74HCT08PW
TSSOP (14)
5.00 mm × 4.40 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
xA
xY
xB
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HCT08, SN74HCT08
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SCLS063F – NOVEMBER 1988 – REVISED OCTOBER 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
(1)
5.2 Recommended Operating Conditions ..................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Switching Characteristics ...........................................5
5.6 Operating Characteristics........................................... 5
6 Parameter Measurement Information............................ 6
7 Detailed Description........................................................7
7.1 Overview..................................................................... 7
7.2 Functional Block Diagram........................................... 7
7.3 Device Functional Modes............................................7
8 Power Supply Recommendations..................................8
9 Layout...............................................................................8
9.1 Layout Guidelines....................................................... 8
9.2 Layout Example.......................................................... 8
10 Device and Documentation Support............................9
10.1 Documentation Support............................................ 9
10.2 Receiving Notification of Documentation Updates....9
10.3 Support Resources................................................... 9
10.4 Trademarks............................................................... 9
10.5 Electrostatic Discharge Caution................................9
10.6 Glossary....................................................................9
11 Mechanical, Packaging, and Orderable
Information...................................................................... 9
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (February 2022) to Revision F (October 2022)
Page
• Increased RθJA for packages: D (86 to 138.7); DB (96 to 114.8); N (80 to 67); NS (76 to 93.3); PW (113 to
159.8)..................................................................................................................................................................4
Changes from Revision D (August 2003) to Revision E (February 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCLS063F – NOVEMBER 1988 – REVISED OCTOBER 2022
4 Pin Configuration and Functions
1A
1
14
VCC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
D, DB, J, N, NS, PW or W Package
14-Pin SOIC, SSOP, PDIP, SO or TSSOP
Top View
FK Package
20-Pin LCCC
Top View
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SCLS063F – NOVEMBER 1988 – REVISED OCTOBER 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
(2)
IIK
Input clamp current
IOK
Output clamp current
IO
Continuous output current
VCC or GND
Continuous current through
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(1)
(2)
MIN
MAX
-0.5
7
UNIT
V
(VI < 0 or VI > VCC)
±20
mA
(VO < 0 or VO > VCC)
±20
mA
(VO = 0 to VCC)
±25
mA
±50
mA
150
°C
150
°C
-65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(1)
5.2 Recommended Operating Conditions
SN54HCT08(2)
SN74HCT08
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
Δt/Δv
Input transition rise/fall time
500
ns
TA
Operating free-air temperature
85
°C
(1)
(2)
2
V
2
V
0.8
500
– 55
125
– 40
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating SMOS Inputs, literature number SCBA004.
SN54HCT08 is in product preview.
5.3 Thermal Information
THERMAL METRIC
DB (SSOP)
N (PDIP)
NS (SO)
PW (TSSOP)
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
UNIT
114.8
67
93.3
159.8
°C/W
55
50.9
92.7
°C/W
RθJA
Junction-to-ambient thermal
(1)
resistance
138.7
RθJC (top)
Junction-to-case (top) thermal
resistance
93.8
RθJB
Junction-to-board thermal
resistance
94.7
63.8
46.7
53.8
102.1
°C/W
ΨJT
Junction-to-top characterization
parameter
49.1
19.7
35.1
17.8
40.4
°C/W
ΨJB
Junction-to-board
characterization parameter
94.3
63.1
46.5
53.3
101.7
°C/W
RθJC (bot)
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
N/A
N/A
°C/W
(1)
4
D (SOIC)
60
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCLS063F – NOVEMBER 1988 – REVISED OCTOBER 2022
5.4 Electrical Characteristics
PARAMETER
TEST CONDITIONS(1)
IOH = –20 μA
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input hold current
VI = VCC or 0
5.5
ICC
Supply current
VI = VCC or 0. IO = 0
5.5
One input at 0.5V or 2.4
V, Other inputs at 0 or
VCC
5.5
ΔICC (2) Supply-current change
Ci
(1)
(2)
(3)
4.5
IOH = –4 mA
IOL = 20 μA
4.5
IOL = 4 mA
MAX
MIN
MAX
SN74HCT08
MIN
TYP
4.4
4.499
4.4
4.4
3.98
4.3
3.7
3.84
MIN
MAX
UNIT
V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
0.33
±0.1
±100
±1000
±1000
nA
2
40
20
μA
1.4
2.4
3
2.9
mA
3
10
10
pF
4.5 to
5.5
Input capacitance
SN54HCT08(3)
TA = 25°C
VCC
(V)
10
V
VI = VIH or VIL, unless otherwise noted.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
SN54HCT08 is in product preview.
5.5 Switching Characteristics
CL = 50 pF. See Parameter Measurement Information
PARAMETER
tpd
Propagation delay
tt
Transition time
(1)
FROM (INPUT)
TO
(OUTPUT)
A or B
Y
Y
VCC
(V)
SN54HCT08(1)
TA = 25°C
MIN
MIN
MAX
SN74HCT08
TYP
MAX
MIN
MAX
4.5
15
24
35
30
5.5
13
22
32
27
4.5
9
15
22
19
5.5
8
14
20
17
ns
ns
SN54HCT08 is in product preview.
5.6 Operating Characteristics
TA = 25°C
Cpd
Power dissipation capacitance per gate
Test Conditions
TYP
UNIT
No load
20
pF
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SCLS063F – NOVEMBER 1988 – REVISED OCTOBER 2022
6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Outputs
3V
Input
1.3V
1.3V
0V
tPLH
(1)
tPHL(1)
VOH
Output
Waveform 1
50%
50%
VOL
tPLH(1)
tPHL(1)
VOH
Output
Waveform 2
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs
6
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SCLS063F – NOVEMBER 1988 – REVISED OCTOBER 2022
7 Detailed Description
7.1 Overview
This device contains four independent 2-input AND Gates. Each gate performs the Boolean function Y = A ● B in
positive logic.
7.2 Functional Block Diagram
xA
xY
xB
Figure 7-1. Functional Block Diagram
7.3 Device Functional Modes
Function Table lists the functional modes of the SN74HCT08.
Table 7-1. Function Table
INPUTS(1)
(1)
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
H = High Voltage Level, L =
Low Voltage Level, X = Don't
Care
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SCLS063F – NOVEMBER 1988 – REVISED OCTOBER 2022
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
9.2 Layout Example
GND
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to
the device
1A
1
14
VCC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
Unused inputs
tied to VCC
Unused output
left floating
Figure 9-1. Example layout for the SN74HCT08
8
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SCLS063F – NOVEMBER 1988 – REVISED OCTOBER 2022
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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9
PACKAGE OPTION ADDENDUM
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20-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74HCT08D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT08
Samples
SN74HCT08DBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT08
Samples
SN74HCT08DE4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT08
Samples
SN74HCT08DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HCT08
Samples
SN74HCT08DRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT08
Samples
SN74HCT08DRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT08
Samples
SN74HCT08N
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT08N
Samples
SN74HCT08NE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT08N
Samples
SN74HCT08NSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT08
Samples
SN74HCT08PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT08
Samples
SN74HCT08PWE4
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT08
Samples
SN74HCT08PWG4
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT08
Samples
SN74HCT08PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HT08
Samples
SN74HCT08PWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT08
Samples
SN74HCT08PWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT08
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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20-Oct-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of