SN54HCT125, SN74HCT125
SCLS069G – NOVEMBER 1988 – REVISED OCTOBER 2022
SNx4HCT125 Quadruple Bus Buffer Gates With 3-State Outputs
1 Features
2 Description
•
•
•
•
•
•
•
•
The SNx4HCT125 contains four independent buffers
with TTL-compatible inputs and 3-state outputs. Each
gate performs the Boolean function Y = A in positive
logic.
Operating voltage range of 4.5 V to 5.5 V
High-current can drive up to 15 LSTTL loads
Low power consumption, 80-µA max ICC
Typical tpd = 12 ns
±6-mA output drive at 5 V
Low input current of 1 µA max
Inputs are TTL-voltage compatible
High-current 3-state outputs drive bus lines or
buffer memory address registers
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HCT125D
SOIC (14)
8.65 mm × 3.90 mm
SN74HCT125N
PDIP (14)
19.31 mm × 6.35 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HCT125, SN74HCT125
www.ti.com
SCLS069G – NOVEMBER 1988 – REVISED OCTOBER 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
(1)
5.2 Recommended Operating Conditions ..................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Switching Characteristics............................................5
5.6 Operating Characteristics........................................... 6
6 Parameter Measurement Information............................ 7
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Device Functional Modes............................................8
8 Power Supply Recommendations..................................9
9 Layout...............................................................................9
9.1 Layout Guidelines....................................................... 9
10 Device and Documentation Support..........................10
10.1 Documentation Support.......................................... 10
10.2 Receiving Notification of Documentation Updates..10
10.3 Support Resources................................................. 10
10.4 Trademarks............................................................. 10
10.5 Electrostatic Discharge Caution..............................10
10.6 Glossary..................................................................10
11 Mechanical, Packaging, and Orderable
Information.................................................................... 10
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2022) to Revision G (October 2022)
Page
• Increased RθJA for packages: D (86 to 138.7); N (80 to 75.3)...........................................................................4
Changes from Revision E (August 2003) to Revision F (February 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect
modern data sheet standards............................................................................................................................. 1
2
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT125 SN74HCT125
SN54HCT125, SN74HCT125
www.ti.com
SCLS069G – NOVEMBER 1988 – REVISED OCTOBER 2022
4 Pin Configuration and Functions
1
14
VCC
2
13
4OE
3
4
12
11
4A
2A
5
10
3OE
2Y
6
7
9
8
1OE
1A
1Y
2OE
GND
4Y
3A
3Y
D, N, J or W Package
14-Pin SOIC or PDIP
Top View
FK Package
20-Pin LCCC
Top View
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT125 SN74HCT125
3
SN54HCT125, SN74HCT125
www.ti.com
SCLS069G – NOVEMBER 1988 – REVISED OCTOBER 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage range
(2)
IIK
Input clamp current
IOK
Output clamp current
IO
Continuous output current
VCC or GND
Continuous current through
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(2)
MIN
MAX
-0.5
7
UNIT
V
(VI < 0 or VI > VCC)
±20
mA
(VO < 0 or VO > VCC)
±20
mA
(VO = 0 to VCC)
±35
mA
±70
mA
150
°C
150
°C
-65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(1)
5.2 Recommended Operating Conditions
SN54HCT125(2)
SN74HCT125
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
tt
Input transition rise/fall time
500
ns
TA
Operating free-air temperature
85
°C
(1)
(2)
2
2
0.8
500
–55
125
–40
V
V
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating SMOS Inputs, literature number SCBA004.
SN54HCT125 is in product preview.
5.3 Thermal Information
THERMAL METRIC
N (PDIP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
138.7
75.3
°C/W
RθJC
Junction-to-case (top) thermal resistance
93.8
68.6
°C/W
RθJB
Junction-to-board thermal resistance
94.7
55.1
°C/W
ψJT
Junction-to-top characterization paramete
49.1
41.1
°C/W
ψJB
Junction-to-board characterization parameter
94.3
54.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
(1)
D (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT125 SN74HCT125
SN54HCT125, SN74HCT125
www.ti.com
SCLS069G – NOVEMBER 1988 – REVISED OCTOBER 2022
5.4 Electrical Characteristics
PARAMETER
TEST CONDITIONS(1)
IOH = –20 μA
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input hold current
IOZ
Off-state output current
ICC
Supply current
ΔICC (2) Supply-current change
One input at 0.5 V or 2.4
V, Other inputs at 0 or
VCC
5.5
Ci
(1)
(2)
(3)
(4)
4.5
IOH = –6 mA
IOL = 20 μA
5.5
IOL = 6 mA
SN54HCT125(3)
TA = 25°C
VCC
(V)
MAX
MIN
MAX
SN74HCT125
MIN
TYP
MIN
4.4
4.499
4.4
4.4
3.98
4.3
3.7
3.84
MAX
UNIT
V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
0.33
±1000
±1000
nA
V
VI = VCC or 0
5.5
±0.1
±100
Vo = VCC or 0
5.5
±0.01
±0.5
±10
±5
μA
VI = VCC or 0. IO = 0
5.5
8
160
80
μA
1.4
2.4
3
2.9
mA
3
10
10(4)
10
pF
4.5 to
5.5
Input capacitance
VI = VIH or VIL, unless otherwise noted.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
SN54HCT125 is in product preview.
On products compliant to MIL-PRF-38535, this parameter is not production tested.
5.5 Switching Characteristics
CL = 50 pF. See Figure 6
PARAMETER
tpd
Propagation delay
ten
FROM
(INPUT)
TO (OUTPUT)
A
Y
Enable time
OE
Y
tdis
Diable time
OE
Y
tt
Transition time
(1)
Any
VCC
(V)
SN54HCT125
TA = 25°C
MIN
(1)
MIN
MAX
SN74HCT125
TYP
MAX
4.5
11
20
39
MIN
MAX
25
5.5
10
18
35
22
4.5
18
28
42
35
5.5
15
25
38
31
4.5
15
26
39
33
5.5
13
23
35
30
4.5
8
15
22
19
5.5
7
14
21
17
SN54HCT125
SN74HCT125
ns
ns
ns
ns
SN54HCT125 is in product preview.
5.5 Switching Characteristics
CL = 150 pF. See Figure 6
PARAMETER
tpd
Propagation delay
ten
Enable time
tt
Transition time
(1)
FROM
(INPUT)
TO (OUTPUT)
A
Y
OE
Y
Any
VCC
(V)
TA = 25°C
MIN
(1)
TYP
MAX
MIN
MAX
MIN
MAX
4.5
19
36
58
46
5.5
16
32
48
42
4.5
25
40
60
50
5.5
21
35
53
43
4.5
17
42
63
53
5.5
14
38
57
48
ns
ns
ns
SN54HCT125 is in product preview.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT125 SN74HCT125
5
SN54HCT125, SN74HCT125
www.ti.com
SCLS069G – NOVEMBER 1988 – REVISED OCTOBER 2022
5.6 Operating Characteristics
TA = 25°C
Cpd
6
Power dissipation capacitance
Test Conditions
TYP
UNIT
No load
35
pF
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT125 SN74HCT125
SN54HCT125, SN74HCT125
www.ti.com
SCLS069G – NOVEMBER 1988 – REVISED OCTOBER 2022
6 Parameter Measurement Information
tpd is the maximum between tPLH and tPHL
tt is the maximum between tTLH and tTHL
Figure 6-1. Load Circuit
Figure 6-2.
Figure 6-3. Voltage Waveforms
Propagation Delay Times
Figure 6-4. Voltage Waveforms
Enable and Disable Times For 3-state Outputs
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when diabled by the
output control.
Waveform 2 is for an output with internal conditions such that the output is high except when diabled by the
output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following charactersitics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT125 SN74HCT125
7
SN54HCT125, SN74HCT125
www.ti.com
SCLS069G – NOVEMBER 1988 – REVISED OCTOBER 2022
7 Detailed Description
7.1 Overview
These bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
7.2 Functional Block Diagram
7.3 Device Functional Modes
Table 7-1. Function Table
(each gate)
INPUTS
8
OUTPUT
OE
A
Y
L
H
H
L
L
L
H
X
Z
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT125 SN74HCT125
SN54HCT125, SN74HCT125
www.ti.com
SCLS069G – NOVEMBER 1988 – REVISED OCTOBER 2022
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT125 SN74HCT125
9
SN54HCT125, SN74HCT125
www.ti.com
SCLS069G – NOVEMBER 1988 – REVISED OCTOBER 2022
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT125 SN74HCT125
PACKAGE OPTION ADDENDUM
www.ti.com
20-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74HCT125D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT125
Samples
SN74HCT125DE4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT125
Samples
SN74HCT125DG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT125
Samples
SN74HCT125DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HCT125
Samples
SN74HCT125DRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT125
Samples
SN74HCT125DT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT125
Samples
SN74HCT125N
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT125N
Samples
SN74HCT125NE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT125N
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of