SN74HCT273DWR

 
     
   SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 Operating Voltage Range of 4.5 V to 5.5 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 12 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 SN54HCT273 . . . FK PACKAGE (TOP VIEW) VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK 2D 2Q 3Q 3D 4D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND CLK 5Q 5D CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND Inputs Are TTL-Voltage Compatible Contain Eight D-Type Flip-Flops Direct Clear Input Applications Include: − Buffer/Storage Registers − Shift Registers − Pattern Generators 1D 1Q CLR VCC SN54HCT273 . . . J OR W PACKAGE SN74HCT273 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) D D D D 8Q D D D D D D description/ordering information These devices are positive-edge-triggered D-type flip-flops with a common enable input. The ’HCT273 devices are similar to the ’HCT377 devices, but feature a common clear enable (CLR) input instead of a latched clock. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. The circuits are designed to prevent false clocking by transitions at CLR. ORDERING INFORMATION PACKAGE† TA PDIP − N SN74HCT273N Tube of 25 SN74HCT273DW Reel of 2000 SN74HCT273DWR SOP − NS Reel of 2000 SN74HCT273NSR HCT273 SSOP − DB Reel of 2000 SN74HCT273DBR HT273 Tube of 70 SN74HCT273PW Reel of 2000 SN74HCT273PWR Reel of 250 SN74HCT273PWT CDIP − J Tube of 20 SNJ54HCT273J SNJ54HCT273J CFP − W Tube of 85 SNJ54HCT273W SNJ54HCT273W LCCC − FK Tube of 55 SNJ54HCT273FK TSSOP − PW −55°C −55 C to 125 125°C C TOP-SIDE MARKING Tube of 20 SOIC − DW −40°C to 85°C ORDERABLE PART NUMBER SN74HCT273N HCT273 HT273 SNJ54HCT273FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated 


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   SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 FUNCTION TABLE (each flip-flop) INPUTS CLR CLK D OUTPUT Q L X X L H ↑ H H H ↑ L L H L X Q0 logic diagram (positive logic) 1D CLK 2D 3 11 3D 4 1D 1D C1 5D 8 1D C1 R CLR 4D 7 1D C1 R 6D 13 1D C1 R 7D 14 1D C1 R 8D 17 1D C1 R 18 1D C1 R C1 R R 1 2 1Q 5 6 2Q 3Q 9 12 4Q 15 5Q 6Q 16 7Q 19 8Q logic diagram, each flip-flop (positive logic) D C C TG TG Q C C C C TG CLK(I) TG C C C C R 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
     
   SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HCT273 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO ∆t/∆v Output voltage 0 High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V SN74HCT273 2 2 Input transition rise/fall time V V 0.8 VCC VCC UNIT 0 0 500 0.8 V VCC VCC V 500 ns V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C MIN TYP MAX SN54HCT273 MIN MAX SN74HCT273 MIN MAX UNIT 4.4 4.499 4.4 4.4 VI = VIH or VIL IOH = −20 µA IOH = −4 mA 4.5 V VOH 4.5 V 3.98 4.30 3.7 3.84 0.001 0.1 0.1 0.1 VI = VIH or VIL IOL = 20 µA IOL = 4 mA 4.5 V VOL 4.5 V 0.17 0.26 0.4 0.33 II ICC VI = VCC or 0 VI = VCC or 0, 5.5 V ±0.1 ±100 ±1000 ±1000 nA 8 160 80 µA 1.4 2.4 3 2.9 mA 3 10 10 10 pF ∆ICC‡ IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC Ci 5.5 V 5.5 V 4.5 V to 5.5 V V V ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.  0 $&'"%$ $#'$ ('! $ # &'"%1# ' #/$ (%# & #1#*("#$+ %'%#' %% %$ #' (#&%$ %'# #/$ /%*+ #,% $'!"#$ '##'1# # '/  %$/# ' $$!# ## ('! -! $#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
 
     
   SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) fclock Clock frequency CLK high or low tw Pulse duration CLR low Data tsu Setup time before CLK↑ CLR inactive th Hold time data after CLK↑ TA = 25°C MIN MAX SN54HCT273 VCC 4.5 V 25 16 20 5.5 V 28 19 23 MIN SN74HCT273 MAX MIN 4.5 V 20 30 25 5.5 V 18 25 22 4.5 V 16 24 20 5.5 V 14 20 17 4.5 V 20 30 25 5.5 V 17 25 21 4.5 V 20 30 25 5.5 V 17 25 21 4.5 V 0 0 0 5.5 V 0 0 0 MAX UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54HCT273 PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN fmax tpd CLR Any tPHL CLR Any tt Any TA = 25°C TYP MAX MIN 4.5 V 25 31 16 5.5 V 28 37 19 MAX UNIT MHz 4.5 V 15 34 50 5.5 V 12 29 42 4.5 V 17 15 50 5.5 V 15 34 42 4.5 V 8 18 22 5.5 V 7 19 21 ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74HCT273 PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd CLR Any tPHL CLR Any tt Any VCC POST OFFICE BOX 655303 MIN 4.5 V 25 31 20 5.5 V 28 37 23 MAX 15 34 42 5.5 V 12 29 36 4.5 V 17 34 42 5.5 V 15 29 36 4.5 V 8 15 19 5.5 V 7 14 17 • DALLAS, TEXAS 75265 UNIT MHz 4.5 V  0 $&'"%$ $#'$ ('! $ # &'"%1# ' #/$ (%# & #1#*("#$+ %'%#' %% %$ #' (#&%$ %'# #/$ /%*+ #,% $'!"#$ '##'1# # '/  %$/# ' $$!# ## ('! -! $#+ 4 TA = 25°C MIN TYP MAX ns ns ns 
 
     
   SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load TYP 30 UNIT pF PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point 3V High-Level Pulse 1.3 V 0V CL = 50 pF (see Note A) tw 1.3 V 1.3 V 0V 3V 1.3 V 3V Low-Level Pulse LOAD CIRCUIT Input 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V 0V tPLH In-Phase Output 1.3 V 10% tPHL 90% 90% tr Out-ofPhase Output tPHL 90% VOH Reference 1.3 V Input 10% V OL tf tPLH 1.3 V 10% 1.3 V 10% 90% tf VOH Data Input 1.3 V 0.3 V 3V 1.3 V 0V tsu 2.7 V VOL tr tr VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES th 2.7 V 3V 1.3 V 0.3 V 0 V tf VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74HCT273DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HT273 SN74HCT273DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273 SN74HCT273DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273 SN74HCT273DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273 SN74HCT273DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273 SN74HCT273DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273 SN74HCT273N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HCT273N SN74HCT273NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273 SN74HCT273PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HT273 SN74HCT273PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HT273 SN74HCT273PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HT273 SN74HCT273PWT ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HT273 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of