SN54HCT273, SN74HCT273
SCLS068G – NOVEMBER 1988 – REVISED JULY 2022
SNx4HCT273 Octal D-Type Flip-Flops With Clear
1 Features
3 Description
•
•
•
•
•
•
•
•
•
These devices are positive-edge-triggered D-type flipflops with a common enable input. The ’HCT273
devices are similar to the ’HCT377 devices, but
feature a common clear enable (CLR) input instead
of a latched clock.
Operating voltage range of 4.5 V to 5.5 V
Outputs can drive up to 10 LSTTL loads
Low power consumption, 80 µA maximum ICC
Typical tpd = 12 ns
±4 mA output drive at 5 V
Low input current of 1 µA maximum
Inputs are TTL-voltage compatible
Contain eight D-type flip-flops
Direct clear input
2 Applications
•
•
•
Buffer or storage registers
Shift registers
Pattern generators
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HCT273DW
SOIC (20)
12.80 mm × 7.50 mm
SN74HCT273DB
SSOP (20)
7.20 mm × 5.30 mm
SN74HCT273N
PDIP (20)
25.40 mm × 6.35 mm
SN74HCT273NS
SO (20)
15.00 mm × 5.30 mm
SN74HCT273PW
TSSOP (20)
6.50 mm × 4.40 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram, (postive logic)
Logic Diagram, Each Flip Flop (positive logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HCT273, SN74HCT273
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SCLS068G – NOVEMBER 1988 – REVISED JULY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 Recommended Operating Conditions(1) .................... 4
6.3 Thermal Information....................................................4
6.4 Electrical Characteristics.............................................5
6.5 Timing Requirements.................................................. 5
6.6 Switching Characteristics............................................6
6.7 Switching Characteristics............................................6
6.8 Operating Characteristics........................................... 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Device Functional Modes............................................8
9 Power Supply Recommendations..................................9
10 Layout.............................................................................9
10.1 Layout Guidelines..................................................... 9
11 Device and Documentation Support..........................10
11.1 Receiving Notification of Documentation Updates.. 10
11.2 Support Resources................................................. 10
11.3 Trademarks............................................................. 10
11.4 Electrostatic Discharge Caution.............................. 10
11.5 Glossary.................................................................. 10
12 Mechanical, Packaging, and Orderable
Information.................................................................... 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2022) to Revision G (July 2022)
Page
• Junction-to-ambient thermal resistance values increased. DW was 58 is now 109.1, DB was 70 is now 122.7,
N was 69 is now 84.6, NS was 60 is now 113.4, PW was 83 is now 131.8........................................................ 4
Changes from Revision E (August 2003) to Revision F (February 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCLS068G – NOVEMBER 1988 – REVISED JULY 2022
5 Pin Configuration and Functions
CLR
1
20
VCC
1Q
2
19
8Q
1D
3
18
8D
2D
4
17
7D
2Q
5
16
7Q
3Q
6
15
6Q
3D
7
14
6D
3Q
8
13
5D
3D
9
12
5Q
10
11
CLK
GND
DB, DW, N, NS, or PW package
20-Pin SSOP, SOIC, PDIP, SO, or TSSOP
(Top View)
FK package
20-Pin LCCC
(Top View)
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SCLS068G – NOVEMBER 1988 – REVISED JULY 2022
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage range
current(2)
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature range
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 Recommended Operating Conditions(1)
SN54HCT273(2)
SN74HCT273
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
Δt/Δv
Input transition rise or fall rate
500
ns/V
TA
Operating free-air temperature
85
°C
(1)
(2)
2
2
V
0.8
500
–55
125
V
–40
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Product Preview
6.3 Thermal Information
THERMAL METRIC
DB (SSOP)
N (PDIP)
NS (SO)
PW (TSSOP)
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
UNIT
109.1
122.7
84.6
113.4
131.8
°C/W
76
81.6
72.5
78.6
72.2
°C/W
RθJA
Junction-to-ambient thermal
(1)
resistance
RθJC(top)
Junction-to-case (top) thermal
resistance
RθJB
Junction-to-board thermal
resistance
77.6
77.5
65.3
78.4
82.8
°C/W
ψJT
Junction-to-top characterization
parameter
51.5
46.1
55.3
47.1
21.5
°C/W
ψJB
Junction-to-board
characterization parameter
77.1
77.1
65.2
78.1
82.4
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
N/A
N/A
°C/W
(1)
4
DW (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCLS068G – NOVEMBER 1988 – REVISED JULY 2022
6.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VI = VIH or VIL
VOL
VI = VIH or VIL
II
VI = VCC or 0
ICC
VI = VCC or 0,
ΔICC (2)
SN54HCT273(1)
TA = 25°C
MIN
TYP
MAX
MIN
MAX
SN74HCT273
MIN
MAX
UNIT
IOH = –20 µA
4.5 V
4.4
4.499
4.4
4.4
IOH = –4 mA
4.5 V
3.98
4.30
3.7
3.84
IOL = 20 µA
4.5 V
0.001
0.1
0.1
0.1
IOL = 4 mA
4.5 V
0.17
0.26
0.4
0.33
5.5 V
±0.1
±100
±1000
±1000
nA
8
160
80
µA
1.4
2.4
3
2.9
mA
3
10
10
10
pF
IO = 0
5.5 V
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
5.5 V
4.5 V to
5V
Ci
(1)
(2)
VCC
V
V
Product Preview
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
6.5 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
fclock
VCC
Clock frequency
CLK high or low
tw
Pulse duration
CLR low
Data
tsu
Setup time before CLK↑
CLR inactive
th
(1)
Hold time, data after CLK↑
SN54HCT273(1)
TA = 25°C
MIN
MAX
MIN
MAX
SN74HCT273
MIN
MAX
4.5 V
25
16
20
5.5 V
28
19
23
4.5 V
20
30
25
5.5 V
18
25
22
4.5 V
16
24
20
5.5 V
14
20
17
4.5 V
20
30
25
5.5 V
17
25
21
4.5 V
20
30
25
5.5 V
17
25
21
4.5 V
0
0
0
5.5 V
0
0
0
UNIT
MHz
ns
ns
ns
Product Preview
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6.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Parameter
Measurement Information)
SN54HCT273(1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLR
Any
tPHL
CLR
Any
tt
(1)
Any
VCC
TA = 25°C
MAX
MIN
MIN
TYP
4.5 V
25
31
16
5.5 V
28
37
19
MAX
UNIT
MHz
4.5 V
15
34
50
5.5 V
12
29
42
4.5 V
17
15
50
5.5 V
15
34
42
4.5 V
8
18
22
5.5 V
7
19
21
ns
ns
ns
Product Preview
6.7 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Parameter
Measurement Information)
SN74HCT273
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLR
Any
tPHL
CLR
Any
tt
Any
VCC
TA = 25°C
MAX
MIN
MIN
TYP
4.5 V
25
31
20
5.5 V
28
37
23
MAX
UNIT
MHz
4.5 V
15
34
42
5.5 V
12
29
36
4.5 V
17
34
42
5.5 V
15
29
36
4.5 V
8
15
19
5.5 V
7
14
17
ns
ns
ns
6.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
6
TEST CONDITIONS
Power dissipation capacitance
No load
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TYP
30
UNIT
pF
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SCLS068G – NOVEMBER 1988 – REVISED JULY 2022
7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 7-1. Load Circuit for Push-Pull Outputs
tw
3V
Clock
Input
3V
Input
1.3V
1.3V
1.3V
0V
0V
tsu
Figure 7-2. Voltage Waveforms, TTL-Compatible
CMOS Inputs Pulse Duration
th
3V
Data
Input
1.3V
1.3V
0V
Figure 7-3. Voltage Waveforms, TTL-Compatible
CMOS Inputs Setup and Hold Times
3V
Input
1.3V
1.3V
0V
tPLH(1)
tPHL(1)
VOH
Output
Waveform 1
50%
50%
VOL
tPHL(1)
tPLH
(1)
VOH
Output
Waveform 2
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-4. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs
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8 Detailed Description
8.1 Overview
These devices are positive-edge-triggered D-type flip-flops with a common enable input. The ’HCT273 devices
are similar to the ’HCT377 devices, but feature a common clear enable (CLR) input instead of a latched clock.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the positive-going pulse. When CLK is at either the high or low level, the D input has no effect
at the output. The circuits are designed to prevent false clocking by transitions at CLR.
8.2 Functional Block Diagram
Figure 8-1. Logic Diagram (positive logic)
Figure 8-2. Logic Diagram, each flip-flop (potitive logic)
8.3 Device Functional Modes
Table 8-1. Function Table
(Each Flip-Flop)
INPUTS
8
CLR
CLK
D
OUTPUT
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Q0
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9 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
10 Layout
10.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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SCLS068G – NOVEMBER 1988 – REVISED JULY 2022
11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74HCT273DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT273
Samples
SN74HCT273DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT273
Samples
SN74HCT273DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT273
Samples
SN74HCT273DWRG4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT273
Samples
SN74HCT273N
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT273N
Samples
SN74HCT273NSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT273
Samples
SN74HCT273PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT273
Samples
SN74HCT273PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT273
Samples
SN74HCT273PWT
ACTIVE
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT273
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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