SN54HCT32, SN74HCT32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS064E – NOVEMBER 1988 – REVISED AUGUST 2003
D
D
D
Operating Voltage Range of 4.5 V to 5.5 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 20-µA Max ICC
D
D
D
D
Typical tpd = 13 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
SN54HCT32 . . . FK PACKAGE
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
NC
2B
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
1A
1B
1Y
2A
2B
2Y
GND
1B
1A
NC
VCC
4B
SN54HCT32 . . . J OR W PACKAGE
SN74HCT32 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
NC – No internal connection
description/ordering information
The ’HCT32 devices contain four independent 2-input OR gates. They perform the Boolean function
A B in positive logic.
Y
A • B or Y
+ )
+
ORDERING INFORMATION
PACKAGE†
TA
PDIP – N
SN74HCT32N
Tube of 50
SN74HCT32D
Reel of 2500
SN74HCT32DR
Reel of 250
SN74HCT32DT
SOP – NS
Reel of 2000
SN74HCT32NSR
HCT32
SSOP – DB
Reel of 2000
SN74HCT32DBR
HT32
Tube of 90
SN74HCT32PW
Reel of 2000
SN74HCT32PWR
TSSOP – PW
–55 C to 125
–55°C
125°C
C
TOP-SIDE
MARKING
Tube of 25
SOIC – D
–40°C
–40
C to 85
85°C
C
ORDERABLE
PART NUMBER
SN74HCT32N
HCT32
HT32
Reel of 250
SN74HCT32PWT
CDIP – J
Tube of 25
SNJ54HCT32J
SNJ54HCT32J
CFP – W
Tube of 150
SNJ54HCT32W
SNJ54HCT32W
LCCC – FK
Tube of 55
SNJ54HCT32FK
SNJ54HCT32FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54HCT32, SN74HCT32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS064E – NOVEMBER 1988 – REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
B
OUTPUT
Y
H
X
H
X
H
H
L
L
L
A
logic diagram (positive logic)
A
Y
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HCT32
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
∆t/∆v
Output voltage
0
High-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
SN74HCT32
MIN
2
2
0.8
Input transition rise/fall time
VCC
VCC
500
0
0
UNIT
V
V
0.8
V
VCC
VCC
V
500
ns
V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54HCT32, SN74HCT32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS064E – NOVEMBER 1988 – REVISED AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VOH
VI = VIH or VIL
IOH = –20 µA
IOH = –4 mA
4.5 V
VOL
VI = VIH or VIL
IOL = 20 µA
IOL = 4 mA
4.5 V
II
ICC
VI = VCC or 0
VI = VCC or 0,
∆ICC†
MIN
MIN
MAX
SN74HCT32
MIN
4.4
4.499
4.4
4.4
4.3
3.7
3.84
5.5 V
4.5 V
to 5.5 V
MAX
UNIT
V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
0.33
±0.1
±100
±1000
±1000
nA
2
40
20
µA
1.4
2.4
3
2.9
mA
3
10
10
10
pF
5.5 V
Ci
SN54HCT32
3.98
5.5 V
IO = 0
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
TA = 25°C
TYP
MAX
V
† This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
tt
Y
VCC
MIN
TA = 25°C
TYP
MAX
SN54HCT32
MIN
MAX
SN74HCT32
MIN
MAX
4.5 V
15
24
35
30
5.5 V
13
22
32
27
4.5 V
9
15
22
19
5.5 V
8
14
20
17
UNIT
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
No load
TYP
20
UNIT
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54HCT32, SN74HCT32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS064E – NOVEMBER 1988 – REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
3V
Test
Point
Input
1.3 V
1.3 V
0V
CL = 50 pF
(see Note A)
tPLH
In-Phase
Output
LOAD CIRCUIT
1.3 V
10%
tPHL
90%
90%
tr
Input 1.3 V
0.3 V
2.7 V
tPHL
3V
2.7 V
1.3 V
0.3 V 0 V
tr
Out-of-Phase
Output
90%
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOH
1.3 V
10% V
OL
tf
tPLH
1.3 V
10%
tf
1.3 V
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Device Marking
(4/5)
SN74HCT32D
ACTIVE
SOIC
D
14
SN74HCT32DBLE
OBSOLETE
SSOP
DB
14
TBD
Call TI
Call TI
-40 to 85
SN74HCT32DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT32
SN74HCT32DBRE4
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT32
SN74HCT32DBRG4
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT32
SN74HCT32DE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT32
SN74HCT32DG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT32
SN74HCT32DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
HCT32
SN74HCT32DRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT32
SN74HCT32DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT32
SN74HCT32DT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT32
SN74HCT32DTE4
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT32
SN74HCT32DTG4
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT32
SN74HCT32N
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT32N
SN74HCT32NE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT32N
SN74HCT32NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT32
SN74HCT32NSRE4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT32
Addendum-Page 1
HCT32
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
18-Oct-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74HCT32NSRG4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT32
SN74HCT32PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT32
SN74HCT32PWE4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT32
SN74HCT32PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT32
SN74HCT32PWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 85
SN74HCT32PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT32
SN74HCT32PWRE4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT32
SN74HCT32PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT32
SN74HCT32PWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT32
SN74HCT32PWTE4
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT32
SN74HCT32PWTG4
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT32
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74HCT32DBR
SSOP
DB
14
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
SN74HCT32DR
SOIC
D
14
2500
330.0
16.8
6.5
9.5
2.3
8.0
16.0
Q1
SN74HCT32DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74HCT32DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74HCT32DRG4
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74HCT32DT
SOIC
D
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74HCT32NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74HCT32PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74HCT32PWT
TSSOP
PW
14
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HCT32DBR
SSOP
DB
14
2000
367.0
367.0
38.0
SN74HCT32DR
SOIC
D
14
2500
364.0
364.0
27.0
SN74HCT32DR
SOIC
D
14
2500
333.2
345.9
28.6
SN74HCT32DR
SOIC
D
14
2500
367.0
367.0
38.0
SN74HCT32DRG4
SOIC
D
14
2500
333.2
345.9
28.6
SN74HCT32DT
SOIC
D
14
250
367.0
367.0
38.0
SN74HCT32NSR
SO
NS
14
2000
367.0
367.0
38.0
SN74HCT32PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74HCT32PWT
TSSOP
PW
14
250
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
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