SN54HCT573, SN74HCT573
SCLS176G – JULY 2003 – REVISED JULY 2022
SNx4HCT573 Octal Transparent D-Type Latches With 3-State Outputs
1 Features
2 Description
•
•
These octal transparent D-type latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance loads.
The ’HCT573 devices are particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
•
•
•
•
•
•
Operating voltage range of 4.5V to 5.5V
High-Current 3-State Outputs Drive Bus Lines
Directly or Up To 15 LSTTL Loads
Low power consumption, 80-µA max ICC
Typical tpd = 21ns
±6-mA output drive at 5V
Low input current of 1µA max
Inputs are TTL-Voltage compatible
Bus-structured pinout
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HCT573DW
SOIC (20)
12.80 mm × 7.50 mm
SN74HCT573DB
SSOP (20)
7.20 mm × 5.30 mm
SN74HCT573N
PDIP (20)
25.40 mm × 6.35 mm
SN74HCT573NS
SO (20)
15.00 mm × 5.30 mm
SN74HCT573PW
TSSOP (20)
6.50 mm × 4.40 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HCT573, SN74HCT573
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SCLS176G – JULY 2003 – REVISED JULY 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
(1)
5.2 Recommended Operating Conditions ..................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Timing Requirements.................................................. 5
5.6 Switching Characteristics ...........................................5
5.7 Operating Characteristics........................................... 6
6 Parameter Measurement Information............................ 7
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Device Functional Modes............................................8
8 Power Supply Recommendations..................................9
9 Layout...............................................................................9
9.1 Layout Guidelines....................................................... 9
10 Device and Documentation Support..........................10
10.1 Documentation Support.......................................... 10
10.2 Receiving Notification of Documentation Updates..10
10.3 Support Resources................................................. 10
10.4 Trademarks............................................................. 10
10.5 Electrostatic Discharge Caution..............................10
10.6 Glossary..................................................................10
11 Mechanical, Packaging, and Orderable
Information.................................................................... 10
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2022) to Revision G (July 2022)
Page
• Junction-to-ambient thermal resistance values increased. DW was 58 is now 109.1, DB was 70 is now 122.7,
N was 69 is now 84.6, NS was 60 is now 113.4, PW was 83 is now 131.8........................................................ 4
Changes from Revision E (July 2003) to Revision F (February 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCLS176G – JULY 2003 – REVISED JULY 2022
4 Pin Configuration and Functions
OE
1
20
VCC
1D
2
19
1Q
2D
3
18
2Q
3D
4
17
3Q
4D
5
16
4Q
5D
6
15
5Q
6D
7
14
6Q
7D
8
13
7Q
8D
9
12
8Q
10
11
LE
GND
J, W, DB, DW, N, NS, or PW package
20-Pin CDIP, CFP, SSOP, SOIC, PDIP, SO, or TSSOP
Top View
FK package
20-Pin LCCC
Top View
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage range
(2)
IIK
Input clamp current
IOK
Output clamp current
IO
Continuous output current
(2)
MIN
MAX
-0.5
7
Junction temperature
Tstg
Storage temperature
(1)
(2)
V
(VI < 0 or VI > VCC)
±20
mA
(VO < 0 or VO > VCC)
±20
mA
(VO = 0 to VCC)
±35
mA
±70
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
UNIT
-65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(1)
5.2 Recommended Operating Conditions
SN54HCT573(2)
SN74HCT573
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
tt
Input transition rise/fall time
500
ns
TA
Operating free-air temperature
85
°C
(1)
(2)
2
V
0.8
500
– 55
V
2
125
– 40
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating SMOS Inputs, literature number SCBA004.
SN54HCT573 is in product preview.
5.3 Thermal Information
THERMAL METRIC
Junction-to-ambient thermal
(1)
resistance
RθJA
DB (SSOP)
N (PDIP)
NS (SO)
PW (TSSOP)
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
UNIT
109.1
122.7
84.6
113.4
131.8
°C/W
76
81.6
72.5
78.6
72.2
RθJC (top)
Junction-to-case (top) thermal
resistance
RθJB
Junction-to-board thermal
resistance
77.6
77.5
65.3
78.4
82.8
ΨJT
Junction-to-top characterization
parameter
51.5
46.1
55.3
47.1
21.5
ΨJB
Junction-to-board
characterization parameter
77.1
77.1
65.2
78.1
82.4
RθJC (bot)
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
N/A
N/A
(1)
4
DW (SOIC)
°C/W
°C/W
°C/W
°C/W
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCLS176G – JULY 2003 – REVISED JULY 2022
5.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TEST
CONDITIONS(1)
PARAMETER
VCC (V)
IOH = – 20 μA
VOH
4.5
IOH = – 6 mA
IOL = 20 μA
VOL
MAX
MIN
SN74HCT573
MIN
TYP
4.4
4.499
4.4
4.4
3.98
4.3
3.7
3.84
4.5
IOL = 6 mA
SN54HCT573(3)
TA = 25°C
MAX
MIN
MAX
UNIT
V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
0.33
±1000
±1000
nA
V
II
VI = VCC or 0
5.5
±0.1
±100
IOZ
VO = VCC or 0
5.5
±0.01
±0.5
±10
±5
μA
ICC
VI = VCC or 0. IO = 0
5.5
8
160
80
μA
ΔICC (2)
One input at 0.5
V or 2.4 V, Other
inputs at 0 or VCC
5.5
1.4
2.4
3
2.9
mA
3
10
10
4.5 to
5.5
Ci
(1)
(2)
(3)
10
pF
VI = VIH or VIL, unless otherwise noted.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
SN54HCT573 is in product preview.
5.5 Timing Requirements
VCC
MIN
tW
Pulse duration, LE high
tsu
Setup time, data before LE↓
th
Hold time, data after LE↓
(1)
SN54HCT573 is in product preview.
SN54HCT573(1)
TA = 25°C
MAX
MIN
MAX
SN74HCT573
MIN
4.5
20
30
25
5.5
17
27
23
4.5
10
15
13
5.5
9
14
12
4.5
5
5
5
5.5
5
5
5
MAX
UNIT
ns
ns
ns
5.6 Switching Characteristics
CL = 50 pF. See Figure 6
PARAM
ETER
FROM (INPUT)
D
TO (OUTPUT)
Q
tpd
LE
Any Q
ten
OE
Any Q
tdis
OE
Any Q
tt
(1)
Any Q
VCC (V)
SN54HCT573(1)
TA = 25°C
MIN
MIN
MAX
SN74HCT573
TYP
MAX
4.5
25
35
53
MIN
MAX
44
5.5
21
32
48
40
4.5
28
35
53
44
5.5
25
32
48
40
4.5
26
35
53
44
5.5
23
32
48
40
4.5
23
35
53
44
5.5
22
32
48
40
4.5
9
12
18
15
5.5
9
11
16
14
ns
ns
ns
ns
SN54HCT573 is in product preview.
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5.6 Switching Characteristics
CL = 150 pF. See Figure 6
PARAM
ETER
FROM (INPUT)
TO (OUTPUT)
D
Q
tpd
ten
LE
Any Q
OE
Any Q
tt
(1)
Any Q
VCC (V)
SN54HCT573(1)
TA = 25°C
MIN
TYP
MAX
MIN
MAX
SN74HCT573
MIN
MAX
4.5
32
52
79
65
5.5
27
47
71
59
4.5
38
52
79
65
5.5
36
47
71
59
4.5
33
52
79
65
5.5
28
47
71
59
4.5
18
42
63
53
5.5
16
38
57
48
ns
ns
ns
SN54HCT573 is in product preview.
5.7 Operating Characteristics
TA = 25°C
Cpd
6
Power dissipation capacitance per latch
Test Conditions
TYP
UNIT
No load
50
pF
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6 Parameter Measurement Information
tpd is the maximum between tPLH and tPHL
Figure 6-1. Load Circuit
Figure 6-2. Voltage Waveforms
Pulse Durations
Figure 6-4. Voltage Waveforms
Propagation Delay and Output Rise and Fall Times
Figure 6-3. Voltage Waveforms
Setup and Hold and Input Rise and Fall Times
Figure 6-5. Voltage Waveforms
Enable and Diable Times for 3-State Outputs
A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when diabled by the
output control.
Waveform 2 is for an output with internal conditions such that the output is high except when diabled by the
output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following charactersitics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
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7 Detailed Description
7.1 Overview
These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive
or relatively low-impedance loads. The ’HCT573 devices are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the
outputs are latched to retain the data that was set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
7.2 Functional Block Diagram
Figure 7-1. Functional Block Diagram
7.3 Device Functional Modes
Function Table
(Each Flip-Flop)
INPUTS
8
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74HCT573DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT573
Samples
SN74HCT573DBRG4
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT573
Samples
SN74HCT573DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT573
Samples
SN74HCT573DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT573
Samples
SN74HCT573DWRG4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT573
Samples
SN74HCT573N
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT573N
Samples
SN74HCT573NSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT573
Samples
SN74HCT573PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT573
Samples
SN74HCT573PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT573
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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