SN74LS04DR










    
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 D Dependable Texas Instruments Quality and Reliability description/ordering information SN5404 . . . J PACKAGE SN54LS04, SN54S04 . . . J OR W PACKAGE SN7404, SN74S04 . . . D, N, OR NS PACKAGE SN74LS04 . . . D, DB, N, OR NS PACKAGE (TOP VIEW) 1A 1Y 2A 2Y 3A 3Y GND These devices contain six independent inverters. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 6A 6Y 5A 5Y 4A 4Y SN5404 . . . W PACKAGE (TOP VIEW) 1A 2Y 2A 1 14 2 13 3 12 VCC 3A 3Y 4A 4 11 5 10 6 9 7 8 1Y 6A 6Y GND 5Y 5A 4Y 1Y 1A NC VCC 6A SN54LS04, SN54S04 . . . FK PACKAGE (TOP VIEW) 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 6Y NC 5A NC 5Y 3Y GND NC 4Y 4A 2A NC 2Y NC 3A NC − No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated     !"   #!$% &"' &!   #" #" (" "  ") !" && *+' &! #", &"  ""%+ %!&" ",  %% #""'  #&! #%  -./.010 %% #"" " ""& !%" ("*" "&'  %% (" #&! #&! #", &"  ""%+ %!&" ",  %% #""' POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 









    
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 ORDERING INFORMATION PDIP − N 0°C 0 C to 70 70°C C ORDERABLE PART NUMBER PACKAGE† TA SOIC − D SOP − NS SSOP − DB CDIP − J −55°C −55 C to 125 125°C C CFP − W LCCC − FK TOP-SIDE MARKING Tube SN7404N SN7404N Tube SN74LS04N SN74LS04N Tube SN74S04N SN74S04N Tube SN7404D Tape and reel SN7404DR Tube SN74LS04D Tape and reel SN74LS04DR Tube SN74S04D Tape and reel SN74S04DR Tape and reel SN7404NSR SN7404 Tape and reel SN74LS04NSR 74LS04 Tape and reel SN74S04NSR 74S04 Tape and reel SN74LS04DBR LS04 Tube SN5404J SN5404J Tube SNJ5404J SNJ5404J Tube SN54LS04J SN54LS04J Tube SN54S04J SN54S04J Tube SNJ54LS04J SNJ54LS04J Tube SNJ54S04J SNJ54S04J Tube SNJ5404W SNJ5404W Tube SNJ54LS04W SNJ54LS04W Tube SNJ54S04W SNJ54S04W Tube SNJ54LS04FK SNJ54LS04FK Tube SNJ54S04FK SNJ54S04FK 7404 LS04 S04 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each inverter) 2 INPUT A OUTPUT Y H L L H POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 









    
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 logic diagram (positive logic) 1A 1Y 2A 2Y 3A 3Y 4A 4Y 5A 5Y 6A 6Y Y=A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 









    
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 schematics (each gate) ’04 VCC 4 kΩ 130 Ω 1.6 kΩ Input A Output Y 1 kΩ GND ’LS04 ’S04 VCC 20 kΩ 120 Ω 8 kΩ Input A VCC 4 kΩ 2.8 kΩ Output Y 50 Ω 900 Ω Input A 3.5 kΩ Output Y 12 kΩ 500 Ω 250 Ω 3 kΩ 1.5 kΩ GND GND Resistor values shown are nominal. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 









    
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI: ’04, ’S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V ’LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN7404 SN5404 VCC VIH Supply voltage VIL IOH Low-level input voltage IOL TA Low-level output current High-level input voltage MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 2 2 High-level output current −55 V V 0.8 0.8 V −0.4 −0.4 mA 16 mA 70 °C 16 Operating free-air temperature UNIT 125 0 NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS‡ PARAMETER VIK VOH VCC = MIN, VCC = MIN, II = − 12 mA VIL = 0.8 V, VOL II VCC = MIN, VCC = MAX, VIH = 2 V, VI = 5.5 V IIH IIL VCC = MAX, VCC = MAX, VI = 2.4 V VI = 0.4 V IOS¶ ICCH VCC = MAX ICCL VCC = MAX, VCC = MAX, MIN SN5404 TYP§ MAX MIN SN7404 TYP§ −1.5 IOH = −0.4 mA IOL = 16 mA 2.4 3.4 0.2 −1.5 2.4 0.4 3.4 0.2 1 −20 VI = 0 V VI = 4.5 V MAX UNIT V V 0.4 1 V mA 40 40 µA −1.6 −1.6 mA −55 mA −55 −18 6 12 6 12 mA 18 33 18 33 mA ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § All typical values are at VCC = 5 V, TA = 25°C. ¶ Not more than one output should be shorted at a time. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 









    
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) TO (OUTPUT) A Y SN5404 SN7404 TEST CONDITIONS MIN RL = 400 Ω, CL = 15 pF UNIT TYP MAX 12 22 8 15 ns recommended operating conditions (see Note 3) SN74LS04 SN54LS04 VCC VIH Supply voltage VIL IOH Low-level input voltage IOL TA High-level input voltage MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 2 2 UNIT V V 0.7 0.8 V High-level output current −0.4 −0.4 mA Low-level output current 4 8 mA 70 °C Operating free-air temperature −55 125 0 NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIK VOH SN54LS04 MIN TYP‡ MAX TEST CONDITIONS† PARAMETER VCC = MIN, VCC = MIN, II = − 18 mA VIL = MAX, SN74LS04 MIN TYP‡ MAX −1.5 IOH = −0.4 mA IOL = 4 mA 2.5 3.4 0.25 −1.5 2.7 3.4 0.4 UNIT V V 0.4 VOL VCC = MIN, VIH = 2 V II IIH VCC = MAX, VCC = MAX, VI = 7 V VI = 2.7 V 0.1 0.1 20 20 µA IIL IOS§ VCC = MAX, VCC = MAX VI = 0.4 V −0.4 −0.4 mA ICCH ICCL VCC = MAX, VCC = MAX, VI = 0 V VI = 4.5 V IOL = 8 mA 0.25 −20 −100 −20 0.5 V mA −100 mA 1.2 2.4 1.2 2.4 mA 3.6 6.6 3.6 6.6 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2) PARAMETER tPLH tPHL 6 FROM (INPUT) TO (OUTPUT) A Y TEST CONDITIONS SN54LS04 SN74LS04 MIN RL = 2 kΩ, POST OFFICE BOX 655303 CL = 15 pF • DALLAS, TEXAS 75265 UNIT TYP MAX 9 15 10 15 ns 









    
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 recommended operating conditions (see Note 3) SN74S04 SN54S04 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current −1 −1 mA IOL TA Low-level output current 20 mA 70 °C High-level input voltage 2 2 V 20 Operating free-air temperature −55 125 V 0 NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS† PARAMETER VIK VOH VCC = MIN, VCC = MIN, II = − 18 mA VIL = 0.8 V, VOL II VCC = MIN, VCC = MAX, VIH = 2 V, VI = 5.5 V IIH IIL VCC = MAX, VCC = MAX, VI = 2.7 V VI = 0.5 V IOS§ ICCH VCC = MAX ICCL VCC = MAX, VCC = MAX, MIN SN54S04 TYP‡ MAX MIN SN74S04 TYP‡ MAX −1.2 IOH = −1 mA IOL = 20 mA 2.5 3.4 −40 VI = 0 V VI = 4.5 V −1.2 2.7 3.4 UNIT V V 0.5 0.5 1 1 V mA 50 50 µA −2 −2 mA −100 mA −100 −40 15 24 15 24 mA 30 54 30 54 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y RL = 280 Ω, CL = 15 pF tPLH tPHL A Y RL = 280 Ω, CL = 50 pF PARAMETER SN54S04 SN74S04 TEST CONDITIONS MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT TYP MAX 3 4.5 3 5 4.5 5 ns ns 7 









    
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION SERIES 54/74 AND 54S/74S DEVICES VCC Test Point VCC RL (see Note B) From Output Under Test CL (see Note A) High-Level Pulse 1.5 V S2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.5 V 1 kΩ Test Point LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS S1 (see Note B) CL (see Note A) RL CL (see Note A) RL From Output Under Test VCC From Output Under Test Test Point 1.5 V 0V tw Low-Level Pulse 1.5 V tsu Data Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS 1.5 V 1.5 V In-Phase Output (see Note D) tPHL VOH 1.5 V Out-of-Phase Output (see Note D) 0V 1.5 V 1.5 V Waveform 1 (see Notes C and D) tPLZ VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ≈1.5 V 1.5 V VOL tPZH tPLH 1.5 V 0V tPZL VOL tPHL 1.5 V 3V Output Control (low-level enabling) 0V tPLH 3V 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input th Waveform 2 (see Notes C and D) VOL + 0.5 V tPHZ VOH 1.5 V VOH − 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 









    
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES VCC Test Point VCC RL From Output Under Test CL (see Note A) CL (see Note A) High-Level Pulse 1.3 V S2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.3 V 5 kΩ Test Point LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS S1 (see Note B) CL (see Note A) RL (see Note B) RL From Output Under Test VCC From Output Under Test Test Point 1.3 V 0V tw Low-Level Pulse 1.3 V tsu 0V In-Phase Output (see Note D) 3V 1.3 V 1.3 V 0V tPZL tPLZ tPHL VOH 1.3 V 1.3 V Waveform 1 (see Notes C and D) VOL tPZH tPLH VOH 1.3 V 1.3 V VOL Waveform 2 (see Notes C and D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ≈1.5 V 1.3 V VOL tPHL Out-of-Phase Output (see Note D) 1.3 V 0V Output Control (low-level enabling) 1.3 V tPLH 1.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.3 V 3V Data Input 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS Input th VOL + 0.5 V tPHZ VOH 1.3 V VOH − 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time, with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) JM38510/00105BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00105BCA JM38510/00105BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00105BDA JM38510/07003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07003BCA JM38510/07003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07003BDA JM38510/30003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 30003B2A JM38510/30003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003BCA JM38510/30003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003BDA JM38510/30003SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003SCA M38510/00105BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00105BCA M38510/00105BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00105BDA M38510/07003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07003BCA M38510/07003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07003BDA M38510/30003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 30003B2A M38510/30003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003BCA M38510/30003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003BDA M38510/30003SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003SCA SN5404J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN5404J Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN54LS04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS04J SN54S04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54S04J SN7404D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404N ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SN7404N SN7404NE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SN7404N SN74LS04D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04DBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS04DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04N ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS04N SN74LS04NE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS04N SN74LS04NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS04 SN74S04D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04N ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SN74S04N SN74S04NE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SN74S04N Addendum-Page 2 LS04 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74S04NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74S04 SNJ5404J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5404J SNJ5404W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5404W SNJ54LS04FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54LS 04FK SNJ54LS04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS04J SNJ54LS04W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS04W SNJ54S04FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54S 04FK SNJ54S04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S04J SNJ54S04W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S04W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of