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SN74LS07
SDLS021D – MAY 1990 – REVISED APRIL 2016
SN74LS07 Hex Buffers and Drivers With Open-Collector High-Voltage Outputs
1 Features
3 Description
•
•
•
These hex buffers and drivers feature high-voltage
open-collector outputs to interface with high-level
circuits or for driving high-current loads. They are
also characterized for use as buffers for driving TTL
inputs. The SN74LS07 devices have a rated output
voltage of 30 V. The maximum sink current is 40 mA.
1
•
Convert TTL Voltage Levels to MOS Levels
High Sink-Current Capability
Input Clamping Diodes Simplify
System Design
Open-Collector Driver for Indicator Lamps
and Relays
2 Applications
•
•
•
•
•
•
•
•
•
•
•
AV Receivers
Audio Docks: Portable
Blu-ray Players and Home Theaters
MP3 Players or Recorders
Personal Digital Assistants (PDA)
Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
Solid-State Drives (SSD): Client and Enterprise
TVs: LCD, Digital, and High-Definition (HDTV)
Tablets: Enterprise
Video Analytics: Server
Wireless Headsets, Keyboards, and Mice
These circuits are compatible with most TTL families.
Inputs are diode-clamped to minimize transmissionline effects, which simplifies design. Typical power
dissipation is 140 mW, and average propagation
delay time is 12 ns.
Device Information(1)
PART NUMBER
PACKAGE (PINS)
BODY SIZE (NOM)
SN74LS07D
SOIC (14)
8.65 mm × 3.90 mm
SN74LS07DB
SSOP (14)
6.20 mm × 5.30 mm
SN74LS07N
PDIP (14)
19.30 mm × 6.35 mm
SN74LS07NS
SO (14)
10.30 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A
Y
Copyright © 2016 Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LS07
SDLS021D – MAY 1990 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 6
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 7
9
Application and Implementation .......................... 8
9.1 Application Information.............................................. 8
9.2 Typical Application .................................................... 8
10 Power Supply Recommendations ....................... 9
11 Layout................................................................... 10
11.1 Layout Guidelines ................................................. 10
11.2 Layout Example .................................................... 10
12 Device and Documentation Support ................. 11
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
11
11
11
11
11
13 Mechanical, Packaging, and Orderable
Information ........................................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (February 2004) to Revision D
Page
•
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
•
Deleted SN54LS07 and SN74LS17 from the data sheet because they are obsolete and no longer supplied ...................... 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
2
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SDLS021D – MAY 1990 – REVISED APRIL 2016
5 Pin Configuration and Functions
D, DB, N, or NS Packages
14-Pin SOIC, SSOP, PDIP, SO
Top View
1A
1
14
V
1Y
2
13
6A
2A
3
12
6Y
2Y
4
11
5A
3A
5
10
5Y
3Y
6
9
4A
GND
7
8
4Y
CC
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
1A
I
Input 1
2
1Y
O
Output 1
3
2A
I
Input 2
4
2Y
O
Output 2
5
3A
I
Input 3
6
3Y
O
Output 3
7
GND
—
Ground pin
8
4Y
O
Output 4
9
4A
I
Input 4
10
5Y
O
Output 5
11
5A
I
Input 5
12
6Y
O
Output 6
13
6A
I
Input 6
14
VCC
—
Power pin
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SN74LS07
SDLS021D – MAY 1990 – REVISED APRIL 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VCC
Supply voltage
(2)
MAX
UNIT
7
V
7
V
VI
Input voltage
VO
Output voltage (2) (3)
30
V
TJ
Operating virtual junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
This is the maximum voltage that should be applied to any output when it is in the off state.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
VOH
High-level output voltage
30
V
IOL
Low-level output current
40
mA
TA
Operating free-air temperature
70
°C
(1)
2
V
0
V
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LS07
THERMAL METRIC
(1)
D
(SOIC)
DB
(SSOP)
N
(PDIP)
NS
(SO)
UNIT
14 PINS
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
85.2
97.4
50.2
82.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
43.5
49.8
37.5
40.9
°C/W
RθJB
Junction-to-board thermal resistance
39.7
44.5
30
41.4
°C/W
ψJT
Junction-to-top characterization parameter
10.9
16.5
22.3
12.4
°C/W
ψJB
Junction-to-board characterization parameter
39.4
44
29.9
41.1
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SDLS021D – MAY 1990 – REVISED APRIL 2016
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
VIK
VCC = MIN, II = –12 mA
IOH
VCC = MIN, VIH = 2 V
VOL
VCC = MIN, VIL = 0.8 V
II
VCC = MAX, VI = 7 V
IIH
VCC = MAX, VI = 2.4 V
20
µA
IIL
VCC = MAX, VI = 0.4 V
–0.2
mA
ICCH
VCC = MAX
14
mA
ICCL
VCC = MAX
45
mA
TYP
MAX
UNIT
6
10
19
30
(1)
(2)
–1.5
V
VOH = 30 V
0.25
mA
IOL = 16 mA
0.4
IOL = MAX (2)
0.7
V
1
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
IOL = 40 mA
6.6 Switching Characteristics
VCC = 5 V, TA = 25°C (see Figure 2)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
A
Y
TEST CONDITIONS
MIN
RL = 110 Ω, CL = 15 pF
ns
6.7 Typical Characteristics
10
9
8
tPLH (ns)
7
6
5
4
3
2
1
0
10
20
30
40
50
Temperature (ƒC)
60
70
C003
Figure 1. tPLH vs. Temperature
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SN74LS07
SDLS021D – MAY 1990 – REVISED APRIL 2016
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7 Parameter Measurement Information
VCC
Test
Point
VCC
RL
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
High-Level
Pulse
1.3 V
5 kΩ
Test
Point
S2
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3V
Timing
Input
1.3 V
S1
(see Note B)
CL
(see Note A)
RL
(see Note B)
RL
From Output
Under Test
VCC
From Output
Under Test
Test
Point
1.3 V
0V
tw
Low-Level
Pulse
tsu
1.3 V
Data
Input
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V
1.3 V
Output
Control
(low-level
enabling)
0V
tPLH
In-Phase
Output
(see Note D)
1.3 V
0V
3V
1.3 V
1.3 V
0V
tPZL
tPLZ
tPHL
VOH
1.3 V
1.3 V
Waveform 1
(see Notes C
and D)
VOL
tPZH
tPLH
VOH
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
≈1.5 V
1.3 V
VOL
tPHL
Out-of-Phase
Output
(see Note D)
3V
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Input
th
VOL + 0.5 V
tPHZ
VOH
Waveform 2
(see Notes C
and D)
1.3 V
VOH − 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
A.
CL includes probe and jig capacitance.
B.
All diodes are 1N3064 or equivalent.
C.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output
control.
D.
S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open
for tPZL.
E.
Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns,
tf ≤ 2.6 ns.
G.
The outputs are measured one at a time, with one input transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
6
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8 Detailed Description
8.1 Overview
The outputs of the SN74LS07 device are open-collector and can be connected to other open-collector outputs to
implement active-low wired-OR or active-high wired-AND functions. The maximum sink current for the SN74LS07
is 40 mA.
Inputs can be driven from 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of this
device as translators in a mixed-system environment.
VCC
1 kΩ
9 kΩ
5 kΩ
Output
Input
2 kΩ
2 kΩ
GND
Copyright © 2016, Texas Instruments Incorporated
Resistor values shown are nominal.
Figure 3. Schematic (Gate)
8.2 Functional Block Diagram
A
Y
Copyright © 2016 Texas Instruments Incorporated
8.3 Feature Description
•
•
Allows for up translation
– Inputs accept voltages to 5.25 V
– Outputs accept voltages to 30 V
High Sink-Current Capability
– Up to 40 mA
8.4 Device Functional Modes
Table 1 lists the functions of this device.
Table 1. Function Table
INPUT A
OUTPUT Y
H
Hi-Z
L
L
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SN74LS07
SDLS021D – MAY 1990 – REVISED APRIL 2016
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LS07 device is a high-drive, open-drain CMOS device that can be used for a multitude of buffer-type
functions. It can produce 40 mA of drive current at 5 V. Therefore, this device is ideal for driving multiple inputs.
The inputs are 5.25-V tolerant and outputs are 30-V tolerant.
9.2 Typical Application
Multiple channels of the SN74LS07 device can be used to create a positive AND logic function, as shown in
Figure 4. Additionally, the SN74LS07 device can be used to drive an LED by sinking up to 40 mA, which may be
more than the previous stage can sink.
SN74LS07
SN74LS07
SN74LS07
Copyright © 2016, Texas Instruments Incorporated
Figure 4. Typical Application Diagram
9.2.1 Design Requirements
Ensure that the inputs are in a known state as defined by VIH and VIL noted in Recommended Operating
Conditions, or else the outputs may be in an unknown state.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For specified high and low level, see VIH and VIL in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as 5.25 V.
2. Recommend Output Conditions
– Load currents must not exceed 40 mA per output.
– Outputs must not be pulled above 30 V.
8
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Typical Application (continued)
9.2.3 Application Curve
15
14.8
14.6
tPHL (ns)
14.4
14.2
14
13.8
13.6
13.4
13.2
13
0
10
20
30
40
50
Temperature (ƒC)
60
70
C004
Figure 5. tPHL vs Temperature
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating indicated in
Recommended Operating Conditions.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
TI recommends a 0.1-µF capacitor; if there are multiple VCC pins, then TI recommends either a 0.01-µF or
0.022-µF capacitor for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different
frequencies of noise. A 0.1-µF and a 1-µF capacitor are commonly used in parallel. The bypass capacitor must
be installed as close to the power pin as possible for best results.
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SN74LS07
SDLS021D – MAY 1990 – REVISED APRIL 2016
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11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins must not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the
part is a transceiver.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
10
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SDLS021D – MAY 1990 – REVISED APRIL 2016
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the followign:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LS07D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
LS07
SN74LS07DBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
LS07
SN74LS07DBRG4
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
LS07
SN74LS07DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
LS07
SN74LS07DRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
LS07
SN74LS07N
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
SN74LS07N
SN74LS07NSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
74LS07
SN74LS07NSRG4
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
74LS07
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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