SN74LS2323D


     SDLS965 − OCTOBER 2004 D Single 5-V Supply D ±100-mV Sensitivity D For Application as: D D D D D D D PACKAGE (TOP VIEW) 1OUT COMSTRB 1LINE GND − Single-Ended Line Receiver − Gated Oscillator − Level Comparator Adjustable Reference Voltage TTL Outputs TTL-Compatible Strobe Designed for Party-Line (Data-Bus) Applications Common Reference-Voltage Pin Common Strobe 1 8 2 7 3 6 4 5 VCC 2OUT COMREF 2LINE description/ordering information This device consists of a dual single-ended line receiver with TTL-compatible strobes and outputs. The reference voltage (switching threshold) is applied externally and can be adjusted from 1.5 V to 3.4 V, making it possible to optimize noise immunity for a given system design. Due to the low input current (less than 100 µA), the device is suited ideally for party-line (data-bus) systems. The SN74LS2323 has a common reference-voltage pin and a common strobe. ORDERING INFORMATION 0°C to 70°C ORDERABLE PART NUMBER PACKAGE† TA SOIC − D Tube SN74LS2323D Tape and reel SN74LS2323DR TOP-SIDE MARKING LS2323 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each receiver) LINE INPUT STROBE OUTPUT ≤(VREF − 100 mV) ≥(VREF + 100 mV) L H X L X H L H = high level, L = low level, X = irrelevant Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated           !" #$ #     %   &  ## '($ # ) #  "( "# )  "" $ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 

     SDLS965 − OCTOBER 2004 logic diagram (positive logic) COMSTRB 1LINE COMREF 2LINE 2 1 1OUT 3 + _ 6 7 5 2OUT + _ schematic (each receiver) VCC VCC 3.5 kΩ VCC VCC VCC VCC 3 kΩ 5.5 kΩ 6 kΩ Line VCC VCC 50 Ω 10 kΩ 2.5 kΩ OUT 1.8 kΩ VREF 1.8 kΩ 20 kΩ 750 Ω VCC 15 kΩ VCC 25 kΩ COMSTRB 2 VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1.5 kΩ 

     SDLS965 − OCTOBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage, VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Line input voltage range with respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2 V to 7 V Line input voltage with respect to VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 V Strobe input voltage, VI(S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Unless otherwise specified, voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN NOM MAX 5 5.5 ‡ V V °C VCC Vref Supply voltage 4.5 Reference input voltage 1.8 VI(L) VI(S) High-level line input voltage 0 High-level strobe input voltage 0 VCC − 1 7 0 70 TA Operating free-air temperature range ‡ Max = VCC−1.5 V u VREF t 3.4 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V V 3 

     SDLS965 − OCTOBER 2004 electrical characteristics over recommended operating VCC = 5 V ±10%, VREF = 1.5 V to 3.5 V (unless otherwise noted) PARAMETER VIH(L) VIL(L) VIH(S) VIL(S) VOH VOL IIH(S) IIH(L) Low-level line input voltage High-level output control input voltage Low-level output control input voltage Low-level output voltage High-level input current High-level input current range, MIN MAX UNIT VI(S) = 0.8 V, IOL = 12 mA, VREF = 2.5 V, VOL ≤ 0.6 V VCC = 4.5 V 2.62 6 VI(S) = 0.8 V, IOL = 16 mA, VREF = 3.4 V, VOL ≤ 0.5 V VCC = 5.5 V 3.5 7 VI(S) = 0.8 V, IOH = −0.4 mA,VREF = 2.5 V, VOH ≥ 2 V VCC = 4.5 V −2 2.38 VI(S) = 0.8 V, IOH = −0.4 mA,VREF = 3.4 V, VOH ≥ 3.2 V VCC = 5.5 V −2 3.3 VI(L) = 1.8 V, VREF = 2.5 V, VO ≤ 0.4 V VI(L) = 1.8 V, VREF = 2.5 V, VO ≥ 2.4 V VCC = 4.5 V VCC = 4.5 V 2 VCC = 4.5 V VCC = 5 V 2 VI(L) = 1.4 V, VI(S) = 0.8 V, IOH = −1 mA, VREF = 2.5 V VI(L) = 3.8 V, VI(S) = 0.8 V, VREF = 2.5 V VI(L) = 3.8 V, VREF = 2.5 V VI(S) = 2.4 V, VREF = 2.5 V V V VCC = 5.5 V VCC = 4.5 V, IOL = 16 mA V 0.8 2.7 V V 2.7 0.6 VCC = 5 V, IOL = 24 mA 0.5 VCC = 5.5 V, IOL = 24 mA 0.5 VCC = 5.5 V, VI(S) = 2.4 V 20 VCC = 5.5 V, VI(S) = 7 V 100 VCC = 5 V, VI(L) = 5 V 100 µA VCC = 5 V, VI(L) = 5.5 V 2 mA V µA A IIH(REF) High-level input current VI(S) = 2.4 V, VREF = 3.4 V VCC = 5.5 V, VI(L) = 2.5 V 500 µA IIL(S) Low-level input current VI(L) = 1.8 V, VREF = 0.1 V VCC = 5.5 V, VI(S) = 0.4 V −400 µA IIL(L) Low-level input current at Line input VI(L) = 0.1 V, VREF = 1.8 V VCC = 5.5 V, VI(S) = 0.4 V −100 µA IIL(REF) Low-level input current at REF pin VI(L) = 1.8 V, VREF = 0.1 V VCC = 5.5 V, VI(S) = 0.4 V −100 µA IOS Short-circuit output current‡ VI(L) = 1.8 V, VREF = 2.8 V VCC = 5.5 V VI(S) = 0.4 V −130 mA ICCH Supply current, output high VI(S) = 0, VCC = 5.5 V VI(L) = VREF − 100 mV 12 mA ICCL Supply current, output low VI(S) = 0, VCC = 5.5 V VI(L) = VREF + 100 mV 16 mA † Only one output should be shorted at a time, and duration of the short circuit should not exceed one second. 4 temperature TEST CONDITIONS High-level line input voltage High-level output voltage free-air POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 −30 

     SDLS965 − OCTOBER 2004 switching characteristics, VCC = 5 V ±10%, VREF = 2.5 V, TA = 0°C to 70°C PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tPLH(L) Propagation delay time, low- to high-level output from LINE CL = 50 pF, RL = 500 Ω, See Figure 1 10 25 35 ns tPHL(L) Propagation delay time, high- to low-level output from LINE CL = 50 pF, RL = 500 Ω, See Figure 1 10 25 35 ns tPLH(S) Propagation delay time, low- to high-level output from COMSTRB CL = 50 pF, RL = 500 Ω, See Figure 1 11 22 ns tPHL(S) Propagation delay time, high- to low-level output from COMSTRB CL = 50 pF, RL = 500 Ω, See Figure 1 8 15 ns † All typical values are at VCC = 5 V, TA = 25°C. PARAMETER MEASUREMENT INFORMATION T.P. 3V VCC 500 W 2.5 V LINE 2V D.U.T. 3V ÎÎÎ COMSTRB CL = 50 pF 1.5 V 1.5 V tPHL(L) 0V tPHL(S) tPLH(L) VOH OUTPUT VOL 0.8 V 2V 0.8 V tPLH(S) 2V VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, tr and tf ≤ 2 ns, and duty cycle = 50%. B. CL includes probe and jig capacitance. C. All diodes are 1N914 (or equivalent). D. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2021 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LS2323DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2021 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LS2323DR SOIC D 8 2500 340.5 336.1 25.0 Pack Materials-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2021, Texas Instruments Incorporated