SN74LS245N

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents SN54LS245, SN74LS245 SDLS146B – OCTOBER 1976 – REVISED SEPTEMBER 2016 SNx4LS245 Octal Bus Transceivers With 3-State Outputs 1 Features 3 Description • • • • These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. 1 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce DC Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns 2 Applications • • • • Building Automation Electronic Point of Sale Factory Automation and Control Test and Measurement The SNx4LS245 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the directioncontrol (DIR) input. The output-enable (OE) input can disable the device so that the buses are effectively isolated. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN54LS245J CDIP (20) 24.20 mm × 6.92 mm SN54LS245W CFP (20) 7.02 mm × 13.72 mm SN54LS245FK LCCC (20) 8.89 mm × 8.89 mm SN74LS245DB SSOP (20) 7.20 mm × 5.30 mm SN74LS245DW SOIC (20) 12.80 mm × 7.50 mm SN74LS245N PDIP (20) 24.33 mm × 6.35 mm SN74LS245NS SO (20) 12.60 mm × 5.30 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) DIR 1 19 A1 OE 2 18 B1 To Seven Other Channels Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. SN54LS245, SN74LS245 SDLS146B – OCTOBER 1976 – REVISED SEPTEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 4 4 4 4 5 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 7 Detailed Description .............................................. 8 9.1 Overview ................................................................... 8 9.2 Functional Block Diagram ......................................... 8 9.3 Feature Description................................................... 8 9.4 Device Functional Modes.......................................... 8 10 Application and Implementation........................ 10 10.1 Application Information.......................................... 10 10.2 Typical Application ............................................... 10 11 Power Supply Recommendations ..................... 12 12 Layout................................................................... 12 12.1 Layout Guidelines ................................................. 12 12.2 Layout Example .................................................... 12 13 Device and Documentation Support ................. 13 13.1 13.2 13.3 13.4 13.5 13.6 Related Links ........................................................ Receiving Notification of Documentation Updates Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 13 13 13 13 13 13 14 Mechanical, Packaging, and Orderable Information ........................................................... 13 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2002) to Revision B Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Deleted Ordering Information table; see POA at the end of the data sheet ......................................................................... 1 • Changed RθJA values in Thermal Information table: 70 to 91.7 for DB package, 58 to 79 for DW package, 69 to 46.1 for N package, and 60 to 74.2 for NS package ...................................................................................................................... 4 2 Submit Documentation Feedback Copyright © 1976–2016, Texas Instruments Incorporated Product Folder Links: SN54LS245 SN74LS245 SN54LS245, SN74LS245 www.ti.com SDLS146B – OCTOBER 1976 – REVISED SEPTEMBER 2016 5 Device Comparison Table TYPE IOL (SINK CURRENT) IOH (SOURCE CURRENT) SN54LS245 12 mA –12 mA SN74LS245 24 mA –15 mA 6 Pin Configuration and Functions J, W, DB, DW, N, or NS Package 20-Pin CDIP, CFP, SSOP, SOIC, PDIP, or SO Top View 18 B1 4 17 B2 A4 5 16 B3 A5 6 15 B4 A6 7 14 B5 A7 8 13 B6 A8 9 12 B7 10 11 B8 GND 3 2 1 OE 3 A3 DIR VCC A2 A3 4 20 19 18 B1 A4 5 17 B2 A5 6 16 B3 A6 7 15 B4 A7 8 14 9 10 11 12 13 B5 B8 B7 B6 OE A1 VCC 19 A2 20 2 A8 1 A1 GND DIR FK Package 20-Pin LCCC Top View Pin Functions PIN NO. NAME I/O DESCRIPTION 1 DIR I 2 A1 I/O Controls signal direction; Low = Bx to Ax, High = Ax to Bx Channel 1, A side 3 A2 I/O Channel 2, A side 4 A3 I/O Channel 3, A side 5 A4 I/O Channel 4, A side 6 A5 I/O Channel 5, A side 7 A6 I/O Channel 6, A side 8 A7 I/O Channel 7, A side 9 A8 I/O Channel 8, A side 10 GND — Ground 11 B8 O/I Channel 8, B side 12 B7 O/I Channel 7, B side 13 B6 O/I Channel 6, B side 14 B5 O/I Channel 5, B side 15 B4 O/I Channel 4, B side 16 B3 O/I Channel 3, B side 17 B2 O/I Channel 2, B side 18 B1 O/I Channel 1, B side 19 OE I 20 VCC — Active low output enable; Low = all channels active, High = all channels disabled (high impedance) Power supply Copyright © 1976–2016, Texas Instruments Incorporated Product Folder Links: SN54LS245 SN74LS245 Submit Documentation Feedback 3 SN54LS245, SN74LS245 SDLS146B – OCTOBER 1976 – REVISED SEPTEMBER 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) MIN VCC Supply voltage (1) VI Input voltage TJ Operating virtual junction temperature Tstg Storage temperature (1) –65 MAX UNIT 7 V 7 V 150 °C 150 °C All voltage values are with respect to GND. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions VCC Supply voltage IOH High-level output current IOL Low-level output current TA Operating free-air temperature MIN NOM MAX SN54LS245 4.5 5 5.5 SN74LS245 4.75 5 5.25 SN54LS245 –12 SN74LS245 –15 SN54LS245 12 SN74LS245 24 SN54LS245 –55 125 SN74LS245 0 70 UNIT V mA mA °C 7.4 Thermal Information SNx4LS245 THERMAL METRIC (1) J (CDIP) W (CFP) FK (LCCC) DB (SSOP) DW (SOIC) N (PDIP) NS (SO) 20 PINS 20 PINS 20 PINS 20 PINS 20 PINS 20 PINS 20 PINS N/A N/A N/A RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 42.3 RθJB Junction-to-board thermal resistance 56.9 (2) ψJT Junction-to-top characterization parameter ψJB RθJC(bot) (1) (2) 4 UNIT 91.7 79.0 46.1 74.2 °C/W (2) 53.1 44.4 32.1 40.4 °C/W 109.5 (2) 45.6 (2) 46.8 46.9 27.0 41.7 °C/W N/A N/A N/A 18.9 18.0 17.6 16.9 °C/W Junction-to-board characterization parameter N/A N/A N/A 46.4 46.3 26.9 41.3 °C/W Junction-to-case (bottom) thermal resistance 15.9 (2) 13.0 (2) 6.7 (2) N/A N/A N/A N/A °C/W (2) 70.1 (2) 46.7 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. MIL-STD-883 for Rth-JCx JEDEC JESD51 for Rth-JB (body not contact PCB) Submit Documentation Feedback Copyright © 1976–2016, Texas Instruments Incorporated Product Folder Links: SN54LS245 SN74LS245 SN54LS245, SN74LS245 www.ti.com SDLS146B – OCTOBER 1976 – REVISED SEPTEMBER 2016 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS (1) PARAMETER VIH MIN High-level input voltage VIL Low-level input voltage VIK Input clamp voltage Hysteresis (VT+ – VT–) TYP (1) MAX 2 VCC = MIN, A or B V SN54LS245 0.7 SN74LS245 0.8 II = –18 mA –1.5 VCC = MIN UNIT 0.2 0.4 2.4 3.4 V V V High-level output voltage VCC = MIN, VIL = VIL(max) VIH = 2 V, IOH = –3 mA VOH Low-level output voltage VCC = MIN, VIH = 2 V, VIL = VIL(max) IOL = 12 mA VOL IOZH Off-state output current, high-level voltage applied VCC = MAX, OE at 2 V VO = 2.7 V 20 µA IOZL Off-state output current, low-level voltage applied VCC = MAX, OE at 2 V VO = 0.4 V –200 µA II Input current at maximum input voltage IIH High-level input current VCC = MAX, VIH = 2.7 V 20 µA IIL Low-level input current VCC = MAX, VIL = 0.4 V –0.2 mA IOS Short-circuit output current (2) VCC = MAX –225 mA A or B VCC = MAX DIR or OE IOH = MAX IOL = 24 mA 0.4 SN74LS245 0.5 VI = 5.5 V 0.1 VI = 7 V 0.1 –40 Total, outputs high ICC Supply current Total, outputs low VCC = MAX Outputs open Outputs at high Z (1) (2) V 2 48 70 62 90 64 95 V mA mA All typical values are at VCC = 5 V, TA = 25°C. Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second. 7.6 Switching Characteristics VCC = 5 V, TA = 25°C (see Figure 2) PARAMETER TEST CONDITIONS tPLH Propagation delay time, low- to high-level output tPHL Propagation delay time, high- to low-level output tPZL Output enable time to low level tPZH Output enable time to high level tPLZ Output disable time from low level tPHZ Output disable time from high level CL = 45 pF, RL = 667 Ω CL = 45 pF, RL = 667 Ω CL = 5 pF, RL = 667 Ω Copyright © 1976–2016, Texas Instruments Incorporated Product Folder Links: SN54LS245 SN74LS245 MIN TYP MAX 8 12 8 12 27 40 25 40 15 25 15 28 Submit Documentation Feedback UNIT ns ns ns 5 SN54LS245, SN74LS245 SDLS146B – OCTOBER 1976 – REVISED SEPTEMBER 2016 www.ti.com 7.7 Typical Characteristics VCC = 5 V, TA = 25°C, CL = 45 pF, RL = 667 Ω 5.5 4.5 Voltage (V) 3.5 2.5 1.5 0.5 Input Output -0.5 0 5 10 Time (ns) 15 20 D001 Figure 1. Simulated Propagation Delay From Input to Output 6 Submit Documentation Feedback Copyright © 1976–2016, Texas Instruments Incorporated Product Folder Links: SN54LS245 SN74LS245 SN54LS245, SN74LS245 www.ti.com SDLS146B – OCTOBER 1976 – REVISED SEPTEMBER 2016 8 Parameter Measurement Information VCC Test Point VCC RL From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS High-Level Pulse 1.3 V 5 kΩ Test Point S2 LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3V Timing Input 1.3 V S1 (see Note B) CL (see Note A) RL (see Note B) RL From Output Under Test VCC From Output Under Test Test Point 1.3 V 0V tw Low-Level Pulse 1.3 V tsu 1.3 V In-Phase Output (see Note D) 3V 1.3 V 1.3 V 0V tPZL tPLZ tPHL VOH 1.3 V 1.3 V Waveform 1 (see Notes C and D) VOL + 0.5 V VOL VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHZ tPZH tPLH ≈1.5 V 1.3 V VOL tPHL Out-of-Phase Output (see Note D) 1.3 V 0V Output Control (low-level enabling) 0V tPLH 1.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.3 V 3V Data Input 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS Input th Waveform 2 (see Notes C and D) VOH 1.3 V VOH – 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms Copyright © 1976–2016, Texas Instruments Incorporated Product Folder Links: SN54LS245 SN74LS245 Submit Documentation Feedback 7 SN54LS245, SN74LS245 SDLS146B – OCTOBER 1976 – REVISED SEPTEMBER 2016 www.ti.com 9 Detailed Description 9.1 Overview The SNx4LS245 uses Schottky transistor logic to perform the standard '245 transceiver function. This standard logic function has a common pinout, direction select pin, and active-low output enable. When the outputs are disabled, the A and B sides of the device are effectively isolated. 9.2 Functional Block Diagram DIR 1 19 A1 OE 2 18 B1 To Seven Other Channels Copyright © 2016, Texas Instruments Incorporated Figure 3. Logic Diagram (Positive Logic) 9.3 Feature Description 9.3.1 3-State outputs The 3-state outputs can drive bus lines directly. All outputs can be put into high impedance mode through the OE pin. 9.3.2 PNP Inputs This device has PNP inputs which reduce dc loading on bus lines. 9.3.3 Hysteresis on Bus Inputs The bus inputs have built-in hysteresis that improves noise margins. 9.4 Device Functional Modes The SNx4LS245 performs the standard '245 logic function. Data can be transmitted from A to B or from B to A depending on the DIR pin value, or the A and B sides can be isolated from one another by setting the OE pin HIGH. 8 Submit Documentation Feedback Copyright © 1976–2016, Texas Instruments Incorporated Product Folder Links: SN54LS245 SN74LS245 SN54LS245, SN74LS245 www.ti.com SDLS146B – OCTOBER 1976 – REVISED SEPTEMBER 2016 Table 1. Function Table INPUTS OE EQUIVALENT OF EACH INPUT DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation TYPICAL OF ALL OUTPUTS VCC VCC 50 Ω NOM 9 kΩ NOM Input Output Figure 4. Schematics of Inputs and Outputs Copyright © 1976–2016, Texas Instruments Incorporated Product Folder Links: SN54LS245 SN74LS245 Submit Documentation Feedback 9 SN54LS245, SN74LS245 SDLS146B – OCTOBER 1976 – REVISED SEPTEMBER 2016 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The SNx4LS245 is commonly used to drive ribbon cables or back plane busses. It allows isolation from the bus when necessary, and increases drive strength on the bus. 10.2 Typical Application Figure 5 shows the SNx4LS245 wired up as a permanently enabled data bus transceiver for both a master and slave device communicating over a ribbon cable or back plane. Master Device Low Drive Strength (MCU, FPGA, CPU) SNx4LS245 SNx4LS245 OE DIR A1 B1 A1 B1 A2 B2 A2 B2 A3 B3 Ribbon Cable A3 B3 A4 B4 or A4 B4 A5 B5 Back Plane A5 B5 A6 B6 A6 B6 A7 B7 A7 B7 A8 B8 A8 B8 DIR OE Slave Device Copyright © 2016, Texas Instruments Incorporated Figure 5. SNx4LS245 Being Used to Communicate Over a Ribbon Cable or Back Plane 10.2.1 Design Requirements This device uses Schottky transistor logic technology. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive creates fast edges into light loads, so routing and load conditions must be considered to prevent ringing. 10.2.2 Detailed Design Procedure • Power Supply – Each device must maintain a supply voltage between 4.5 V and 5.5 V • Inputs – Input signals must meet the VIH and VIL specifications in Electrical Characteristics – Inputs leakage values (II, IIH, IIL) from Electrical Characteristics must be considered • Outputs – Output signals are specified to meet the VOH and VOL specifications in Electrical Characteristics as a minimum (the values could be closer to VCC for high signals or GND for low signals) – TI recommends maintaining output currents as specified in Recommended Operating Conditions – The part can be damaged by sourcing or sinking too much current. See Electrical Characteristics for details. 10 Submit Documentation Feedback Copyright © 1976–2016, Texas Instruments Incorporated Product Folder Links: SN54LS245 SN74LS245 SN54LS245, SN74LS245 www.ti.com SDLS146B – OCTOBER 1976 – REVISED SEPTEMBER 2016 Typical Application (continued) 10.2.3 Application Curve It is common to see significant losses in ribbon cables and back planes. Figure 6 shows a simplified simulation of a ribbon cable from a 5-V, 10-MHz low-drive strength source. It shows the difference between an input signal from a weak driver like an MCU or FPGA compared to a strong driver like the SN74LS245 when measured at the distant end of the cable. By adding a high-current drive transceiver before the cable, the signal strength can be significantly improved, and subsequently the cable can be longer. 5.5 Unbuffered SN74LS245 4.5 Voltage (V) 3.5 2.5 1.5 0.5 -0.5 0 100 200 300 Time (ns) 400 500 D001 Unbuffered line is directly connected to low current source, SN74LS245 line is buffered through the transceiver. Both signals are measured at the distant end of the ribbon cable. Input signal is not shown. Figure 6. Simulated Outputs From Ribbon Cable With a 5-V, 10-MHz Source Copyright © 1976–2016, Texas Instruments Incorporated Product Folder Links: SN54LS245 SN74LS245 Submit Documentation Feedback 11 SN54LS245, SN74LS245 SDLS146B – OCTOBER 1976 – REVISED SEPTEMBER 2016 www.ti.com 11 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in Recommended Operating Conditions. Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends a 0.1-µF bypass capacitor. If there are multiple VCC pins, TI recommends a 0.01-µF or 0.022-µF bypass capacitors for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. Two bypass capacitors of value 0.1 µF and 1 µF are commonly used in parallel. For best results, install the bypass capacitor(s) as close to the power pin as possible. 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices, inputs must not be left floating. In many applications, some channels of the SNx4LS245 are unused, and thus must be terminated properly. Because each transceiver channel pin can be either an input or an output, they must be treated as both when being terminated. Ground or VCC (whichever is more convenient) can be used to terminate unused inputs; however, each unused channel should be terminated to the same logic level on both the A and B side. For example, in Figure 7 unused channels 4, 5, 6, and 7 are terminated correctly with both sides connected to the same voltage, while channel 8 is terminated incorrectly with each side being tied to a different voltage. The OE input is also unused in this example, and is terminated directly to ground to permanently enable all outputs. 12.2 Layout Example DIR Device 1 SNx4LS245 OE A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 GND Correctly Terminated Device 2 VCC Incorrectly Terminated Figure 7. Example Demonstrating How to Terminate Unused Inputs and Channels of a Transceiver 12 Submit Documentation Feedback Copyright © 1976–2016, Texas Instruments Incorporated Product Folder Links: SN54LS245 SN74LS245 SN54LS245, SN74LS245 www.ti.com SDLS146B – OCTOBER 1976 – REVISED SEPTEMBER 2016 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN54LS245 Click here Click here Click here Click here Click here SN74LS245 Click here Click here Click here Click here Click here 13.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 13.3 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 1976–2016, Texas Instruments Incorporated Product Folder Links: SN54LS245 SN74LS245 Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-8002101VSA ACTIVE CFP W 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8002101VS A SNV54LS245W 80021012A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 80021012A SNJ54LS 245FK 8002101SA ACTIVE CFP W 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8002101SA SNJ54LS245W Samples JM38510/32803B2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 32803B2A Samples JM38510/32803BRA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 32803BRA Samples JM38510/32803BSA ACTIVE CFP W 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 32803BSA Samples M38510/32803B2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 32803B2A Samples M38510/32803BRA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 32803BRA Samples M38510/32803BSA ACTIVE CFP W 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 32803BSA Samples SN54LS245J ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN54LS245J Samples SN74LS245DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS245 Samples SN74LS245DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS245 Samples SN74LS245DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS245 Samples SN74LS245N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS245N Samples SN74LS245NE4 ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS245N Samples SN74LS245NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74LS245 Samples SNJ54LS245FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 80021012A SNJ54LS Samples Addendum-Page 1 Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 245FK SNJ54LS245J ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SNJ54LS245J Samples SNJ54LS245W ACTIVE CFP W 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8002101SA SNJ54LS245W Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of