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SN74LS292, SN74LS294
SDLS153A – JANUARY 1981 – REVISED JANUARY 2016
SN74LS29x Programmable Frequency Dividers and Digital Timers
1 Features
3 Description
•
•
The SN74LS29x devices are programmable
frequency dividers and digital timers contain 31 flipflops plus 30 gates (in SN74LS292) or 15 flip-flops
plus 29 gates (in SN74LS294) on a single chip. The
count modulo is under digital control of the inputs
provided.
1
•
•
Count Divider Chain
Digitally Programmable from 22 to 2n
(n = 31 for SN74LS292 , n = 15 for SN74LS294)
Useable Frequency Range from DC to 30 MHz
Easily Expandable
Both types feature an active-low CLR clear input to
initialize the state of all flip-flops. To facilitate the
incoming inspection, test points are provided (TP1,
TP2, and TP3 on the SN74LS292, and TP on the
SN74LS294). These test points are not intended to
drive system loads. Both types feature two clock
inputs; either one may be used for clock gating (see
Table 1).
2 Applications
•
•
Frequency Division
Digital Timing
A brief look at the digital timing capabilities of the
SN74LS292 shows that with a 1-MHz input
frequency, programming for 210 gives a period of
1.024 ms, 220 gives a period of 1.05 sec, 226 gives a
period of 1.12 min, and 231 gives a period of 35.79
min.
These devices are easily cascadable, giving limitless
possibilities to achievable timing delays.
Device Information(1)
PART NUMBER
PACKAGE
SN74LS292N
PDIP (16)
SN74LS294N
BODY SIZE (NOM)
6.35 mm × 19.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Symbols
'LS292
CLR
CLK1
CLK2
11
é fi ù
ê nú
ë2 û
R
1
4
5
3
n=0
fi
6
13
n=1
A
B
C
D
E
10
1
TP2
TP3
0
0
éënùû
31
15
14
2
TP1
4
é fi ù
ê fo n ú
ë 2 û
7
Q
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LS292, SN74LS294
SDLS153A – JANUARY 1981 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
5
5
5
6
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
7
Parameter Measurement Information .................. 7
8
Detailed Description ............................................ 10
7.1 Logic Diagrams ......................................................... 7
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (January 1981) to Revision A
Page
•
Removed SN54LS292 and SN54LS294 from the data sheet ................................................................................................ 1
•
Added ESD Ratings and Thermal Information tables, Feature Description section, Device Functional Modes section,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
2
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SDLS153A – JANUARY 1981 – REVISED JANUARY 2016
5 Pin Configuration and Functions
SN74LS29x J, W, or N Package
16-Pin PDIP
Top View
B
E
TP 1
CLK 1
CLK 2
TP 2
Q
1
16
2
15
GND
8
3
4
5
6
7
VCC
C
14 D
13 TP 3
12 NC
11 CLR
10 A
9 NC
Pin Functions, SN74LS292
PIN
NAME
PDIP
I/O
DESCRIPTION
A
10
I
Programming input A
B
1
I
Programming input B
C
15
I
Programming input C
CLK1
4
I
Clock 1 input
CLK2
5
I
Clock 2 input
CLR
11
I
Active-low clear input
D
14
I
Programming input D
E
2
I
Programming input E
GND
8
-
Ground
9, 12
-
No connect
Q
7
O
Q Output
TP
—
O
Test Point
TP1
3
O
Test Point
TP2
6
O
Test Point
TP3
13
O
Test Point
VCC
16
-
Power
NC
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Pin Functions, SN74LS294
PIN
NAME
I/O
PDIP
DESCRIPTION
A
2
I
Programming input A
B
1
I
Programming input B
C
15
I
Programming input C
CLK1
4
I
Clock 1 input
CLK2
5
I
Clock 2 input
CLR
11
I
Active-low clear input
D
14
I
Programming input D
E
—
I
Programming input E
GND
8
-
Ground
6, 9 ,10, 12, 13
-
No connect
Q
7
O
Q Output
TP
3
O
Test Point
TP1
—
O
Test Point
TP2
—
O
Test Point
TP3
—
O
Test Point
VCC
16
-
Power
NC
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VCC
(2)
MAX
UNIT
Supply voltage
7
V
Input voltage
7
V
150
°C
150
°C
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage values are with respect to network ground terminal.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current (Q only)
IOL
Low-level output current (Q only)
fclock
Clock frequency
tw
Duration of clock input pulse
tw
Duration of clear pulse
tsu
Clear inactive-state set-up time
15
TA
Operating free-air temperature
0
4
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2
0
V
0.8
V
–1.2
mA
24
mA
30
MHz
16
SN74LS292
55
SN74LS294
35
ns
ns
ns
70
°C
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SDLS153A – JANUARY 1981 – REVISED JANUARY 2016
6.3 Thermal Information
SN74LS292
THERMAL METRIC (1)
N (PDIP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
36.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
22.2
°C/W
RθJB
Junction-to-board thermal resistance
17.0
°C/W
ψJT
Junction-to-top characterization parameter
7.0
°C/W
ψJB
Junction-to-board characterization parameter
16.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.4 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
VIK
MIN
TYP (2)
VCC = MIN, II = –18 mA
VOH
Q
Q
VOL
VCC = MIN, VIH = 2 V, IOH = –1.2 mA, VIL = MAX
VCC = MIN, VIH = 2 V, VIL = MAX
TP (3)
2.4
MAX
UNIT
–1.5
V
3.4
V
IOL = 12 mA
0.25
0.4
IOL = 24 mA
0.35
0.5
IOL = 0.5 mA
0.25
0.4
V
II
VCC = MAX, VI = 7 V
0.1
mA
IIH
VCC = MAX, VI = 2.7 V
20
mA
CLK1, CLK2
VCC = MAX, VI = 0.4 V
–0.8
All others
VCC = MAX, VI = 0.4 V
–0.4
Q
VCC = MAX
SN74LS292
VCC = MAX, all inputs grounded, all outputs open
40
75
SN74LS294
VCC = MAX, all inputs grounded, all outputs open
30
50
IIL
IOS (4)
ICC
(1)
(2)
(3)
(4)
–30
–130
mA
mA
mA
For conditions shown as MIN or MAX, use the appropriate value specified under Recommended Operating Conditions.
All typical values are at VCC = 5 V, TA = 25°C.
The TP output or outputs are not intended to drive external loads, but are solely provided for test points.
The duration of the short-circuit should not exceed one second.
6.5 Switching Characteristics
VCC = 5 V, TA = 25°C, RL = 667 Ω, CL = 45 pF (see Figure 1)
PARAMETER
fmax
TEST CONDITIONS
From CLK1 or 2
MIN
TYP
30
50
MAX
UNIT
MHz
2
tPLH
From CLK1 or 2, to Q; Modulo set at 2 , A through # = LLLHL
(xxxxLS292), A through D = LLHL (xxxxLS294)
55
90
80
120
SN74LS292
85
130
SN74LS294
35
65
ns
2
From CLK1 or 2, to Q; Modulo set at 2 , A through # = LLLHL
(xxxxLS292), A through D = LLHL (xxxxLS294)
tPHL
From CLR, to Q
ns
VCC
RL= 667W
From Output
Under Test
CL= 45 pF
Figure 1. Switching Loads
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CLR
CLK1
Q22
Q23
CLK2
Figure 2. Timing Diagram
6.6 Typical Characteristics
0.6
0.5
0.4
VCC
@4.75V
V OL
(typ) V
0.3
0.2
0.1
0
3
6
9
12
15
18
21
24
27
30
I OL (mA)
Figure 3. VOL vs IOL
6
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SDLS153A – JANUARY 1981 – REVISED JANUARY 2016
7 Parameter Measurement Information
7.1 Logic Diagrams
'LS292
CLR
CLK1
CLK2
11
é fi ù
ê nú
ë2 û
R
1
4
5
3
n=0
fi
6
13
n=1
A
B
C
D
E
10
1
TP2
TP3
0
0
éënùû
31
15
14
2
TP1
4
é fi ù
ê fo n ú
ë 2 û
7
Q
These symbols are in accordance with ANSi/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are
for J, N, and W packages.
Figure 4. Logic Symbols
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Logic Diagrams (continued)
'LS292
CLR
CLK1
CLK2
11
4
5
R
R
T
T
R
X/Y
T
2D R
2T
M2
0
R
T
28
26
24
22
A
B
C
D
E
3
2D R
R
2T
M2
T
20
18
16
10
1
2
15
4
14
8
2
16
14
6
2D R
R
2T
T
TP1
TP2
M2
2D R
12
10
8
13
2T
TP3
M2
R
T
6
4
2
2D
R
2T
T
M2
2D R
2T
S
3D
3T
7
Q
M2
M3
Pin numbers shown are for J, N, and W packages.
Figure 5. Logic Diagram (Positive Logic) SN74LS292
8
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Logic Diagrams (continued)
'LS294
CLR
CLK1
CLK2
11
4
R
R
T
T
5
X/Y
2D R
0
2T
1
14
13
M2
12
11
10
9
8
A
B
C
D
2
1
15
14
3
TP1
1
2
4
8
2D R
2T
M2
7
6
5
4
3
2
3D S
3T
7
Q
M3
Pin numbers shown are for J, N, and W packages.
Figure 6. Logic Diagram (Positive Logic) SN74LS294
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8 Detailed Description
8.1 Overview
Functional Block Diagram shows that the count modulo is controlled by an X/Y decoder connected to the mode
control inputs of several flip-flops. These flip-flops with mode controls each have a D input connected to the
parallel clock line, and a T input driven by the preceding stage. The parallel clock frequency is always the input
frequency divided by four.
The X/Y decoder output selected by the programming inputs goes low. While a mode control is slow, the D input
of that flip-flop is enabled, and the signal from the parallel clock line (fin ÷ 4) is passed to the T input of the
following stage. All the other mode controls are high, enabling the T inputs and causing each flip-flop in turn to
divide by two.
8.2 Functional Block Diagram
Parallel Clock
Active E-Low Clear
2D
Output of
Preceding Stage
From X/Y
Coder
2T
M2
R
To Toggle
Input of
Next Stage
8.3 Feature Description
This SN74LS29x device can be used to digitally program from 22 to 2n (n = 31 for SN74LS292, n = 15 for
SN74LS294) divider chain. This has a useable frequency range up to 30 MHz. The flexibility is offered when the
devices are cascaded to have desired timing delay.
8.4 Device Functional Modes
Table 1, Table 2, and Table 3 list the functional modes of the SN74LS292.
Table 1. Function Table
10
CLEAR
CLK1
CLK2
Q OUTPUT MODE
L
X
X
Cleared to L
H
↑
L
Count
H
L
↑
Count
H
H
X
Inhibit
H
X
H
Inhibit
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Table 2. SN74LS292 Function Table
FREQUENCY DIVISION
PROGRAMMING INPUTS
Q
TP1
TP2
TP3
E
D
C
B
A
BINARY
DECIMAL
BINARY
DECIMAL
BINARY
DECIMAL
BINARY
DECIMAL
L
L
L
L
L
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
L
L
L
L
H
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
2
9
17
24
L
L
L
H
L
2
4
2
512
2
131072
2
16777216
L
L
L
H
H
23
8
29
512
217
131072
224
16777216
L
L
H
L
L
24
16
29
512
217
131072
224
16777216
5
9
17
24
L
L
H
L
H
2
32
2
512
2
131072
2
16777216
L
L
H
H
L
26
64
29
512
217
131072
224
16777216
L
L
H
H
H
27
128
29
512
217
131072
224
16777216
L
H
L
L
L
8
256
9
512
17
131072
2
2
9
2
9
2
17
2
2
4
L
H
L
L
H
2
512
2
512
2
131072
2
4
L
H
L
H
L
210
1024
29
512
217
131072
24
16
L
H
L
H
H
211
2048
29
512
217
131072
24
16
12
9
17
6
64
L
H
H
L
L
2
4096
2
512
2
131072
2
L
H
H
L
H
213
8192
29
512
217
131072
26
64
L
H
H
H
L
214
16384
29
512
Disabled low
Disabled low
28
256
L
H
H
H
H
215
32768
29
512
Disabled low
Disabled low
28
256
L
L
16
2
65536
9
2
512
2
8
210
1024
8
210
1024
12
4096
3
H
L
L
H
L
L
L
H
217
131072
29
512
23
H
L
L
H
L
18
262144
9
512
5
2
19
2
9
2
5
32
2
12
H
L
L
H
H
2
524288
2
512
2
32
2
4096
H
L
H
L
L
220
1048576
29
512
27
128
214
16384
H
L
H
L
H
221
2097152
29
512
27
22
128
214
16384
9
16
65536
H
L
H
H
L
2
4194304
Disabled low
Disabled low
2
512
2
H
L
H
H
H
223
8388608
Disabled low
Disabled low
29
512
216
65536
H
H
L
L
L
224
16777216
23
8
211
2048
218
262144
H
H
L
L
H
225
33554432
23
8
211
2048
218
262144
26
5
13
8192
220
1048576
8192
220
1048576
22
4194304
H
H
L
H
L
2
67108864
2
H
H
H
L
H
H
227
134217728
25
H
H
L
L
28
268435456
7
2
29
2
7
32
2
32
213
128
15
2
15
32768
2
22
H
H
H
L
H
2
536870912
2
128
2
32768
2
4194304
H
H
H
H
L
230
1073741824
29
512
217
131072
224
16777216
H
H
H
H
H
231
2147483648
29
512
217
131072
224
16777216
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Table 3. SN74LS294 Function Table
FREQUENCY DIVISION
PROGRAMMING INPUTS
Q
TP
D
C
B
A
BINARY
DECIMAL
BINARY
DECIMAL
L
L
L
L
Inhibit
Inhibit
Inhibit
Inhibit
L
L
L
H
Inhibit
Inhibit
Inhibit
Inhibit
L
L
H
L
22
4
29
512
3
9
L
L
H
H
2
8
2
512
L
H
L
L
24
16
29
512
L
H
L
H
25
32
29
512
6
9
L
H
H
L
2
64
L
H
H
H
27
128
H
L
L
L
28
256
22
4
H
L
L
H
9
512
3
8
4
2
10
512
2
Disabled Low
2
H
L
H
L
2
1024
2
16
H
L
H
H
211
2048
25
32
H
H
L
L
212
4096
26
64
13
7
H
H
L
H
2
8192
2
128
H
H
H
L
214
16384
28
256
H
H
H
H
215
32768
29
512
Figure 7, Figure 9, and Figure 9 show the schematics of inputs and outputs of the SN74LS292.
VCC
VCC
100 Ω
Req
INPUT
OUTPUT
Figure 7. Equivalent of Each Input
Figure 8. Typical of Q Outputs
OUTPUT
Figure 9. Typical of TP Outputs
12
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This device is used for configurable frequency, programmable frequency, and timing division as shown in Typical
Application.
9.2 Typical Application
5V
0.1 F
VCC
CLR
A
Control
B
Q
976Hz
Phase detector
1024
C
D
1MHz
TP
16
CLK
Oscillator
Z>^294
GND
Figure 10. Typical application
9.2.1 Design Requirements
This device does not have balanced output drive. Take care to avoid bus contention because it can sink currents
that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load
conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– Rise time and fall time specs. See (Δt/ΔV) in Recommended Operating Conditions.
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions.
– Inputs can go as high as (VI max) in Recommended Operating Conditions at any valid VCC.
2. Recommended Output Conditions:
– Load currents should not exceed (IOH,IOL) per output. These limits are located in the Recommended
Operating Conditions.
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Product Folder Links: SN74LS292 SN74LS294
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SN74LS292, SN74LS294
SDLS153A – JANUARY 1981 – REVISED JANUARY 2016
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Typical Application (continued)
9.2.3 Application Curve
0.5
0.4
VCC
@ 4.75 V
VOL
(max) V
0.3
0.2
0.1
0
3
6
9
12
15
18
21
24
27
I OL (mA)
Figure 11. VOL vs IOL
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended and, if there are multiple VCC pins, then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused (for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used). Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states.
The following are the rules that must be observed under all circumstances:
• All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from
floating.
• The logic level that must be applied to any particular unused input depends on the function of the device.
Generally they are tied to GND or VCC, whichever make more sense or is more convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Output
Unused Input
Input
Figure 12. Generic Layout Best Practices
14
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Copyright © 1981–2016, Texas Instruments Incorporated
Product Folder Links: SN74LS292 SN74LS294
SN74LS292, SN74LS294
www.ti.com
SDLS153A – JANUARY 1981 – REVISED JANUARY 2016
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Digital Phase-Locked Loop Design Using SN74LS297, SDLA005
• Introduction to Logic, SLVA700
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN74LS292
Click here
Click here
Click here
Click here
Click here
SN74LS294
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1981–2016, Texas Instruments Incorporated
Product Folder Links: SN74LS292 SN74LS294
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
SN74LS292N
ACTIVE
PDIP
N
16
25
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
0 to 70
SN74LS292N
SN74LS294N
ACTIVE
PDIP
N
16
25
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
0 to 70
SN74LS294N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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