SN74LV125D


    
  
 
  
SCES003B − NOVEMBER 1994 − REVISED APRIL 1996 D EPIC ( Enhanced-Performance Implanted D D D D CMOS) 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC, TA = 25°C ESD Protection Exceeds 2000 V per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs 1OE 1A 1Y 2OE 2A 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y SN54LV125 . . . FK PACKAGE (TOP VIEW) 1A 1OE NC VCC 4OE D SN54LV125 . . . J OR W PACKAGE SN74LV125 . . . D, DB, OR PW PACKAGE (TOP VIEW) 1Y NC 2OE NC 2A description These quadruple bus buffer gates are designed for 2.7-V to 5.5-V VCC operation. 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3OE 2Y GND NC 3Y 3A The ’LV125 feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. 4 NC − No internal connection The SN54LV125 is characterized for operation over the full military temperature range of −55°C to 125°C. The SN74LV125 is characterized for operation from −40°C to 85°C. FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright  1996, Texas Instruments Incorporated 


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SCES003B − NOVEMBER 1994 − REVISED APRIL 1996 logic symbol† 1OE 1A 2OE 2A 3OE 3A 4OE 4A 1 2 4 5 logic diagram (positive logic) EN 1 3 6 1OE 1Y 1A 13 12 8 11 2 3 1Y 2Y 10 9 1 2OE 4 3Y 2A 5 6 2Y 4Y 3OE † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, DB, J, PW, and W packages. 3A 4OE 4A 10 9 8 3Y 13 12 11 4Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 70 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): D package . . . . . . . . . . . . . . . . . . . 1.25 W DB or PW package . . . . . . . . . . . . 0.5 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 

    
  
 
  
SCES003B − NOVEMBER 1994 − REVISED APRIL 1996 recommended operating conditions (see Note 4) SN54LV125 VCC Supply voltage MIN MAX MIN MAX 2.7 5.5 2.7 5.5 VIH High-level input voltage VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VI VO Input voltage 0 Output voltage 0 IOH High-level output current VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V IOL Low-level output current VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V ∆t /∆V Input transition rise or fall rate TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating. SN74LV125 2 2 3.15 3.15 0.8 0.8 1.65 0 0 V V 1.65 VCC VCC UNIT VCC VCC −8 −8 −16 −16 8 8 16 16 V V V mA mA 0 100 0 100 ns / V −55 125 −40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VCC† IOH = − 100 µA IOH = − 8 mA MIN to MAX‡ IOH = − 16 mA IOL = 100 µA 4.5 V 3V SN54LV125 MIN TYP† II VI = VCC or GND IOZ VO = VCC or GND ICC VI = VCC or GND, nICC One input at VCC − 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND Co VO = VCC or GND IO = 0 MAX MIN VCC −0.2 2.4 VCC −0.2 2.4 3.6 3.6 MIN to MAX‡ IOL = 8 mA IOL = 16mA SN74LV125 TYP† MAX UNIT V 0.2 0.2 3V 0.4 0.4 4.5 V 0.55 0.55 3.6 V ±1 ±1 5.5 V ±1 ±1 3.6 V ±5 ±5 5.5 V ±5 ±5 3.6 V 20 20 5.5 V 20 20 3 V to 3.6 V 500 500 3.3 V 3.5 3.5 5V 3.5 3.5 3.3 V 8 8 5V 8 8 V µA A µA A µA A µA pF pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. )  '*"+%("' #"'#&+' ,+"!$# ' & *"+%(4& "+ !&3' ,(& "* !&4&.",%&'/ )(+(#&+# !(( ('! "&+ ,&#*#("' (+& !&3' 3"(./ &0( '+$%&' +&&+4& & +3 " #('3& "+ !#"''$& && ,+"!$# 1"$ '"#&/ • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 

    
  
 
  
SCES003B − NOVEMBER 1994 − REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LV125 PARAMETER tpd ten FROM (INPUT) TO (OUTPUT) VCC = 5.5 V ± 0.5 V MIN TYP† MAX VCC = 3.3 V ± 0.3 V MIN TYP† MAX VCC = 2.7 V MIN UNIT MAX A Y 7 18 9 19 23 ns OE Y 5 19 7 25 31 ns Y 7 17 9 23 28 ns tdis OE † All typical values are at VCC = 3.3 V, TA = 25°C. switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74LV125 PARAMETER tpd ten FROM (INPUT) TO (OUTPUT) VCC = 5.5 V ± 0.5 V MIN TYP† MAX VCC = 3.3 V ± 0.3 V MIN TYP† MAX VCC = 2.7 V MIN UNIT MAX A Y 7 18 9 19 23 ns OE Y 5 19 7 25 31 ns Y 7 17 9 23 28 ns tdis OE † All typical values are at VCC = 3.3 V, TA = 25°C. operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS Outputs enabled 3.3 V Outputs disabled Cpd Power dissipation capacitance Outputs enabled CL = 50 pF, Outputs disabled )  '*"+%("' #"'#&+' ,+"!$# ' & *"+%(4& "+ !&3' ,(& "* !&4&.",%&'/ )(+(#&+# !(( ('! "&+ ,&#*#("' (+& !&3' 3"(./ &0( '+$%&' +&&+4& & +3 " #('3& "+ !#"''$& && ,+"!$# 1"$ '"#&/ 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • VCC f = 10 MHz 5V TYP 45 5 48 5 UNIT pF pF 

    
  
 
  
SCES003B − NOVEMBER 1994 − REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION S1 1 kΩ From Output Under Test Vz Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Vz GND 1 kΩ WAVEFORM CONDITION Vm Vi Vz LOAD CIRCUIT VCC = 4.5 V to 5.5 V 0.5 × VCC VCC 2 × VCC VCC = 2.7 V to 3.6 V 1.5 V 2.7 V 6V Vi Vm Timing Input 0V tw tsu Vi Input Vm th Vi Vm Vm Data Input Vm 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Vi Vm Input 0V VOH Vm Output Vm VOL Output VOH Vm 0V Vm VOL tPLZ Output Waveform 1 S1 at Vz (see Note B) tPLH tPHL Vm Vm tPZL tPHL tPLH Vi Output Control Vm Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Vm tPZH 0.5 × Vz VOL + 0.3 V VOL tPHZ Vm VOH − 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74LV125D OBSOLETE SOIC D 14 TBD Call TI Call TI Samples Not Available SN74LV125DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI Samples Not Available SN74LV125DR OBSOLETE SOIC D 14 TBD Call TI Call TI Samples Not Available SN74LV125PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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