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SN74LV1T08DBVR

SN74LV1T08DBVR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOT23-5

  • 描述:

    单电源2输入正与门CMOS逻辑电平移位器

  • 数据手册
  • 价格&库存
SN74LV1T08DBVR 数据手册
SN74LV1T08 SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 SN74LV1T08 Single Power Supply 2-Input Positive AND Gate CMOS Logic Level Shifter 1 Features • • • • • • • • • • • • • Single-supply voltage translator at 5.0-V, 3.3-V, 2.5-V, and 1.8-V VCC Operating range of 1.8 V to 5.5 V Up translation: – 1.2 V(1) to 1.8 V at 1.8-V VCC – 1.5 V(1) to 2.5 V at 2.5-V VCC – 1.8 V(1) to 3.3 V at 3.3-V VCC – 3.3 V to 5.0 V at 5.0-V VCC Down translation: – 3.3 V to 1.8 V at 1.8-V VCC – 3.3 V to 2.5 V at 2.5-V VCC – 5.0 V to 3.3 V at 3.3-V VCC Logic output is referenced to VCC Output drive: – 8 mA Output Drive at 5 V – 7 mA Output Drive at 3.3 V – 3 mA Output Drive at 1.8 V Characterized up to 50 MHz at 3.3-V VCC 5 V tolerance on input pins –40°C to 125°C operating temperature range Pb-free packages available: SC-70 (DCK) – 2 × 2.1 × 0.65 mm (height 1.1 mm) Latch-up performance exceeds 250 mA Per JESD 17 Supports standard logic pinouts CMOS output B compatible with AUP1G and LVC1G families 1 2 Applications • • • • Telecom Portable applications Servers PC and notebooks 3 Description The SN74LV1T08 is a single 2-input AND gate with reduced input thresholds to support voltage translation applications. Device Information PART NUMBER SN74LV1T08 (1) (1) PACKAGE BODY SIZE (NOM) DBV (SOT-23, 5) 2.90 mm × 1.60 mm DCK (SC70, 5) 2.00 mm × 1.25 mm For all available packages, see the orderable addendum at the end of the data sheet. Vcc = 3.3V 5.0V, 3.3V 2.5V, 1.8V System LV1Txx Logic 3.3V System VOH min = 2.4V VIH min = 1.36V VIL min = 0.8V VOL max = 0.4V Switching Thresholds for 1.8-V to 3.3-V Translation 1 Refer to the VIH/VIL and output drive for lower VCC condition. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LV1T08 www.ti.com SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Related Products............................................................. 3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings........................................ 5 7.2 ESD Ratings............................................................... 5 7.3 Recommended Operating Conditions.........................6 7.4 Thermal Information....................................................6 7.5 Electrical Characteristics.............................................6 7.6 Switching Characteristics............................................7 7.7 Operating Characteristics........................................... 8 7.8 Typical Characteristics................................................ 8 8 Parameter Measurement Information............................ 9 9 Detailed Description......................................................10 9.1 Overview................................................................... 10 9.2 Functional Block Diagram......................................... 10 9.3 Feature Description...................................................10 9.4 Device Functional Modes..........................................12 10 Power Supply Recommendations..............................13 11 Layout........................................................................... 13 11.1 Layout Guidelines................................................... 13 12 Device and Documentation Support..........................14 12.1 Receiving Notification of Documentation Updates..14 12.2 Support Resources................................................. 14 12.3 Trademarks............................................................. 14 12.4 Electrostatic Discharge Caution..............................14 12.5 Glossary..................................................................14 13 Mechanical, Packaging, and Orderable Information.................................................................... 14 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (February 2014) to Revision C (June 2022) Page • Added ESD Ratings table, Thermal Information table, Typical Characteristics section, Pin Configuration and Functions section, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Receiving Notification of Documentation Updates section, and Community Resources section........................................................................................................................... 1 • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Added Thermal Information table....................................................................................................................... 6 • Added Typical Characteristics............................................................................................................................ 8 Changes from Revision A (September 2013) to Revision B (February 2014) Page • Updated document formatting. .......................................................................................................................... 1 • Updated document formatting............................................................................................................................ 1 • Added ESD Ratings table, Thermal Information table, Typical Characteristics section, Pin Configuration and Functions section, Detailed Description section, Power Supply Recommendations section, Layout section, Receiving Notification of Documentation Updates section, and Community Resources section....................... 5 • Updated Electrical characteristics table..............................................................................................................6 • Removed Ioh test condition for Voh parameter ................................................................................................... 6 • Removed Ioh = -2.3mA for Vol parameter ...........................................................................................................6 Changes from Revision * (September 2013) to Revision A (September 2013) Page • Updated VCC values for VIH parameter in the Electrical Characteristics table....................................................6 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV1T08 SN74LV1T08 www.ti.com SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 5 Related Products DEVICE PACKAGE DESCRIPTION SN74LV1T00 DCK, DBV 2-Input Positive-NAND Gate SN74LV1T02 DCK, DBV 2-Input Positive-NOR Gate SN74LV1T04 DCK, DBV Inverter Gate SN74LV1T08 DCK, DBV 2-Input Positive-AND Gate SN74LV1T17 DCK, DBV Single Schmitt-Trigger Buffer Gate SN74LV1T14 DCK, DBV Single Schmitt-Trigger Inverter Gate SN74LV1T32 DCK, DBV 2-Input Positive-OR Gate SN74LV1T34 DCK, DBV Single Buffer Gate SN74LV1T86 DCK, DBV Single 2-Input Exclusive-Or Gate SN74LV1T125 DCK, DBV Single Buffer Gate with 3-state Output SN74LV1T126 DCK, DBV Single Buffer Gate with 3-state Output SN74LV4T125 RGY, PW Quadruple Bus Buffer Gate With 3-State Outputs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV1T08 3 SN74LV1T08 www.ti.com SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 6 Pin Configuration and Functions A 1 B 2 GND 3 5 VCC 4 Y Figure 6-1. DCK or DBV Package, 5-Pin SC70 or SOT-23 (Top View) Table 6-1. Pin Functions PIN NAME TYPE(1) DESCRIPTION A 1 I Input A B 2 I Input B GND 3 G Ground Y 4 O Output Y VCC 5 P Positive supply (1) 4 NO. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV1T08 SN74LV1T08 www.ti.com SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC VI MIN MAX Supply voltage range –0.5 7.0 V range(2) –0.5 7.0 V –0.5 4.6 V –0.5 VCC + 0.5 Input voltage Voltage range applied to any output in the high-impedance or power-off state(2) VO Voltage range applied to any output in the high or low state(2) UNIT V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current ±25 mA Continuous current through VCC or GND ±50 mA TJ Junction temperature 150 °C Tstg Storage temperature 150 °C (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 7.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC V(ESD) Electrostatic discharge JS-001(1) Machine Model (MM), per JEDEC specification Charged-device model (CDM), per ANSI/ESDA/JEDEC (1) (2) ±2000 ±200 JS-002(2) UNIT V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV1T08 5 SN74LV1T08 www.ti.com SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage VI Input voltage VO Output voltage IOH High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature MIN MAX 1.6 5.5 V 0 5.5 V 0 VCC V VCC = 1.8 V –3 VCC = 2.5 V –5 VCC = 3.3 V –7 VCC = 5.0 V –8 VCC = 1.8 V 3 VCC = 2.5 V 5 VCC = 3.3 V 7 VCC = 5.0 V 8 VCC = 1.8 V 20 VCC = 3.3 V or 2.5 V 20 VCC = 5.0 V (1) UNIT mA mA ns/V 20 –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 7.4 Thermal Information THERMAL METRIC(1) RθJA (1) Junction-to-ambient thermal resistance DBV DCK 5 PINS 5 PINS 206 252 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH VIL 6 TEST CONDITIONS High-level input voltage Low-level input voltage VCC TA = 25°C MIN TYP TA = –40°C to +125°C MAX MIN VCC = 1.65 V to 1.8 V 0.94 1.0 VCC = 2.0 V 1.02 1.03 VCC = 2.25 V to 2.5 V 1.135 1.18 VCC = 2.75 V 1.21 1.23 VCC = 3 V to 3.3 V 1.35 1.37 VCC = 3.6 V 1.47 1.48 VCC = 4.5 V to 5.0 V 2.02 2.03 VCC = 5.5 V 2.1 TYP MAX V 2.11 VCC = 1.65 V to 2.0 V 0.58 0.55 VCC = 2.25 V to 2.75 V 0.75 0.71 VCC = 3 V to 3.6 V 0.8 0.65 VCC = 4.5 V to 5.5 V 0.8 0.8 Submit Document Feedback UNIT V Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV1T08 SN74LV1T08 www.ti.com SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –20 µA IOH = –2.3 mA IOH = –3 mA IOH = –5.5 mA VOL ΔICC 1.93 2.25 2.15 2.78 2.7 2.6 2.49 2.9 2.8 4.2 4.1 4.1 3.95 4.6 0.1 0.1 IOL = 1.9 mA 1.65 V 0.2 0.25 4.5 0.1 0.15 2.3 V IOL = 3 mA IOL = 3 mA 0.15 0.2 0.1 0.15 0.2 0.252 3.0 V Static supply VI = 0 V or VCC, IO = 0; open on loading current One input at 0.3 V or 3.4 V, Other inputs at 0 or VCC, Additional IO = 0 static supply One input at 0.3 V or 1.1 V current Other inputs at 0 or VCC, IO = 0 V 0.15 0.2 0.3 0.35 0.12 ±1 5.0 V 1 10 3.3 V 1 10 2.5 V 1 10 1.8 V 1 10 5.5 V 1.35 1.5 mA 1.8 V 10 10 μA 10 pF 4.5 V A input; VI = 0 V or VCC UNIT V 1.65 V to 5.5 V IOL = 8 mA ICC 2.0 2.0 IOL = 20 µA IOL = 4 mA Input leakage current 1.45 2.0 MAX 5.0 V IOL = 5.5 mA II 1.5 TYP IOH = –8 mA IOL =2.3 mA Low-level output voltage 1.21 1.8 V 4.5 V IOH = –8 mA MIN VCC – 0.1 3.3 V IOH = –4 mA MAX 1.28 3.0 V IOH = –5.5 mA TYP VCC – 0.1 2.5 V IOH = –3.0 mA TA = –40°C to +125°C 1.65 V 2.3 V IOH = –3 mA High-level output voltage MIN 1.65 V to 5.5 V IOH = –2.0 mA VOH TA = 25°C VCC 0 V, 1.8 V, 2.5 V, 3.3 V, 5.5 V Ci Input VI = VCC or GND capacitance 3.3 V 2 Co Output VO = VCC or GND capacitance 3.3 V 2.5 10 2 2.5 μA μA pF 7.6 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Parameter Measurement Information) PARAMETER FROM (INPUT) TO (OUTPUT) FREQUENCY (TYP) VCC 5.0 V DC to 50 MHz 3.3 V tpd Any In Y DC to 25 MHz 2.5 V DC to 15 MHz 1.8 V CL TA = 25°C MIN TYP TA = –65°C to 125°C MAX MIN TYP MAX 15 pF 4 5 4 5 30 pF 5.5 7.0 5.5 7.0 15 pF 4.8 5 5 5.5 30 pF 5 5.5 5.5 6.5 15 pF 6 6.5 7 7.5 30 pF 6.5 7.5 7.5 8.5 15 pF 10.5 11 11 12 30 pF 12 13 12 14 UNIT ns ns ns ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV1T08 7 SN74LV1T08 www.ti.com SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 7.7 Operating Characteristics TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance f = 1 MHz and 10 MHz VCC TYP 1.8 V ± 0.15 V 10 2.5 V ± 0.2 V 10 3.3 V ± 0.3 V 10 5.5 V ± 0.5 V 10 UNIT pF 7.8 Typical Characteristics Figure 7-1. Excellent Signal Integrity (1.8 V to 3.3 V at 3.3-V VCC) Figure 7-2. Excellent Signal Integrity (3.3 V to 3.3 V at 3.3-V VCC) Figure 7-3. Excellent Signal Integrity (3.3 V to 1.8 V at 1.8-V VCC) 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV1T08 SN74LV1T08 www.ti.com SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 8 Parameter Measurement Information From Output Under Test CL (see Note A) VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VI/2 VCC/2 5, 10, 15, 30 pF VI/2 VCC/2 1 MΩ CL VMI VMO LOAD CIRCUIT VI VMI Input VMI 0V tPHL tPLH VOH VMO Output VMo VOL tPHL tPLH VOH Output VMo VMo VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. B. C. D. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tpd. Figure 8-1. Load Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV1T08 9 SN74LV1T08 www.ti.com SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 9 Detailed Description 9.1 Overview The SN74LV1T08 device is a low-voltage CMOS gate logic that operates at a wider voltage range for industrial, portable, telecom, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to match 1.8 V input logic at VCC = 3.3 V and can be used in 1.8 V to 3.3 V level-up translation. In addition, the 5 V tolerant input pins enable down translation (that is, 3.3 V to 2.5 V output at VCC = 2.5 V). The wide VCC range of 1.8 V to 5.5 V allows generation of desired output levels to connect to controllers or processors. The SN74LV1T08 device is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs. 9.2 Functional Block Diagram A B 1 4 2 Y Figure 9-1. Logic Diagram 9.3 Feature Description 9.3.1 Clamp Diode Structure The outputs to this device have both positive and negative clamping diodes, and the inputs to this device have negative clamping diodes only as depicted in Figure 9-2. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed. Device VCC +IOK Input Output Logic -IIK -IOK GND Figure 9-2. Electrical Placement of Clamping Diodes for Each Input and Output 9.3.2 Balanced CMOS Push-Pull Outputs This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink and source similar currents. The drive capability of this device may create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. Unused push-pull CMOS outputs should be left disconnected. 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV1T08 SN74LV1T08 www.ti.com SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 9.3.3 LVxT Enhanced Input Voltage The SN74LV1T08 belongs to TI's LVxT family of Logic devices with integrated voltage level translation. This family of devices was designed with reduced input voltage thresholds to support up-translation, and inputs tolerant of signals with up to 5.5 V levels to support down-translation. The output voltage will always be referenced to the supply voltage (VCC), as described in the Electrical Characteristics table. To ensure proper functionality, input signals must remain at or below the specified VIH(MIN) level for a HIGH input state, and at or below the specified VIL(MAX) for a LOW input state. Figure 9-3 shows the typical VIH and VIL levels for the LVxT family of devices, as well as the voltage levels for standard CMOS devices for comparison. The inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I). The inputs require that input signals transition between valid logic states quickly, as defined by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification will result in excessive power consumption and could cause oscillations. More details can be found in the Implications of Slow or Floating CMOS Inputs application report. Do not leave inputs floating at any time during operation. Unused inputs must be terminated at VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down resistor can be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; however, a 10-kΩ resistor is recommended and will typically meet all requirements. 3.6 3.4 3.3-V CMOS 3.2 VIH 3 VIL HIGH Input 2.8 LOW Input 2.6 2.5-V CMOS 2.4 2.4 V (VOH) VIN - Input Voltage (V) 2.2 2 2 V (VOH) 1.8-V CMOS 1.8 1.6 1.45 V (VOH) 1.4 1.2 1.2-V CMOS 1.1 V (VOH) 1 0.8 0.6 0.45 V (VOL) 0.4 0.4 V (VOL) 0.4 V (VOL) 0.3 V (VOL) 0.2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.5 VCC - Supply Voltage (V) Figure 9-3. LVxT Input Voltage Levels 9.3.3.1 Down Translation Signals can be translated down using the SN74LV1T08. The voltage applied at the VCC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and 0 V in the LOW state. Ensure that the input signals in the HIGH state are between VIH(MIN) and 5.5 V, and input signals in the LOW state are lower than VIL(MAX) as shown in Figure 9-3. For example, standard CMOS inputs for devices operating at 5.0 V, 3.3 V or 2.5 V can be down-translated to match 1.8 V CMOS signals when operating from 1.8-V VCC. See Figure 9-4. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV1T08 11 SN74LV1T08 www.ti.com SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 Down Translation Combinations: • 1.8-V VCC – Inputs from 2.5 V, 3.3 V, and 5.0 V • 2.5-V VCC – Inputs from 3.3 V and 5.0 V • 3.3-V VCC – Inputs from 5.0 V 9.3.3.2 Up Translation Input signals can be up translated using the SN74LV1T08. The voltage applied at VCC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and 0 V in the LOW state. The inputs have reduced thresholds that allow for input high-state levels which are much lower than standard values. For example, standard CMOS inputs for a device operating at a 5-V supply will have a VIH(MIN) of 3.5 V. For the SN74LV1T08, VIH(MIN) with a 5-V supply is only 2 V, which would allow for up-translation from a typical 2.5-V to 5-V signals. Ensure that the input signals in the HIGH state are above VIH(MIN) and input signals in the LOW state are lower than VIL(MAX) as shown in Figure 9-4. Up Translation Combinations: • 1.8-V VCC – Inputs from 1.2 V • 2.5-V VCC – Inputs from 1.8 V • 3.3-V VCC – Inputs from 1.8 V and 2.5 V • 5.0-V VCC – Inputs from 2.5 V and 3.3 V VIH = 2.0 V VIL = 0.8 V 5.0 V 3.3 V System VIH = 0.99 V VIL = 0.5 V Vcc = 5.0 V 5.0 V, 3.3 V 2.5 V, 1.8 V 1.5 V, 1.2 V System 5.0 V System LV1Txx Logic Vcc = 1.8 V LV1Txx Logic 1.8 V System Figure 9-4. LVxT Up and Down Translation Example 9.4 Device Functional Modes Function Table INPUT(1) (LOWER LEVEL INPUT) OUTPUT(2) (VCC CMOS) A B Y H H H L X L L L X SUPPLY VCC = 3.3 V A B VIH(min) = 1.35 V VIL(max) = 0.08 V (1) (2) 12 Y VOH(min) = 2.9 V VOL(max) = 0.2 V H = High Voltage Level, L = Low Voltage Level, X = Do not Care, Z = High Impedance H = Driving High, L = Driving Low, Z = High Impedance State Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV1T08 SN74LV1T08 www.ti.com SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the following layout example. 11 Layout 11.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV1T08 13 SN74LV1T08 www.ti.com SCLS739C – SEPTEMBER 2013 – REVISED JUNE 2022 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV1T08 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LV1T08DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (NEE3, NEEJ, NEES) SN74LV1T08DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 NEE3 SN74LV1T08DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (WE3, WEJ, WES) SN74LV1T08DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM WE3 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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库存:0

SN74LV1T08DBVR
  •  国内价格 香港价格
  • 3000+0.966103000+0.11985
  • 6000+0.931436000+0.11555
  • 9000+0.914089000+0.11339
  • 15000+0.8948515000+0.11101
  • 21000+0.8835921000+0.10961
  • 30000+0.8727930000+0.10827
  • 75000+0.8494975000+0.10538

库存:12301

SN74LV1T08DBVR
    •  国内价格
    • 1+0.69850
    • 200+0.48070
    • 1500+0.43780

    库存:2655