参考文献
SN74LV1T34
ZHCSBY2E – DECEMBER 2013 – REVISED FEBRUARY 2024
SN74LV1T34 单电源单缓冲器门 CMOS 逻辑电平转换器
1 特性
•
•
•
•
•
•
•
•
•
闩锁性能超过 250mA，符合 JESD 17 规范
5V、3.3V、2.5V 和 1.8V VCC 的单电源电压转换器
工作电压范围为 1.65V 至 5.5V
升压转换：
– 1.8V VCC 时，1.2V(1) 至 1.8V
– 2.5V VCC 时，1.5V(1) 至 2.5V
– 3.3V VCC 时，1.8V(1) 至 3.3V
– 5.0V VCC 时，3.3V 至 5.0V
降压转换：
– 1.8V VCC 时，3.3V 至 1.8V
– 2.5V VCC 时，3.3V 至 2.5V
– 3.3V VCC 时，5.0V 至 3.3V
逻辑输出以 VCC 为基准
输出驱动：
– 电压为 5V 时，输出驱动为 8mA
– 电压为 3.3V 时，输出驱动为 7mA
– 电压为 1.8V 时，输出驱动为 3mA
3.3V VCC 时，频率高达 50MHz
输入引脚可耐受 5V 电压
VIH = 2.0V
VIL = 0.8V
5.0V
3.3V
System
• -40°C 至 125°C 工作温度范围
• 支持标准逻辑引脚排列
• 与 AUP1G 和 LVC1G 系列兼容的 CMOS 输出 B1
2 应用
•
•
•
•
电信
便携式应用
服务器
PC 和笔记本电脑
3 说明
SN74LV1T34 是一款具有低输入阈值的单路缓冲门，
可支持电压转换应用。
封装信息
封装(1)
器件型号
SN74LV1T34
(1)
(2)
(3)
DBV（SOT-23，5） 2.90mm × 2.8mm
2.90mm × 1.60mm
DCK（SC70，5）
2.00mm × 1.25mm
VIH = 0.99V
VIL = 0.55V
5.0V, 3.3V
2.5V, 1.8V
1.5V, 1.2V
System
5.0V
System
封装尺寸(3)
2.00mm × 2.1mm
有关更多信息，请参阅第 12 节。
封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。
封装尺寸（长 x 宽）为标称值，不包括引脚。
Vcc = 5.0V
LV1Txx Logic
封装(2)
Vcc = 1.8V
1.8V
System
LV1Txx Logic
Vcc = 3.3V
5.0V, 3.3V
2.5V, 1.8V
System
LV1Txx Logic
3.3V
System
VOH min = 2.4V
VIH min = 1.36V
VIL min = 0.8V
VOL max = 0.4V
1.8V 至 3.3V 转换的开关阈值
1
请参考较低 VCC 条件下的 VIH/VIL 和输出驱动。
本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认
准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。
English Data Sheet: SCLS743
SN74LV1T34
www.ti.com.cn
ZHCSBY2E – DECEMBER 2013 – REVISED FEBRUARY 2024
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Related Products............................................................. 3
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................7
6.7 Operating Characteristics........................................... 7
6.8 Typical Characteristics................................................ 8
7 Parameter Measurement Information............................ 9
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
2
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................12
9 Application and Implementation.................................. 13
9.1 Power Supply Recommendations.............................13
9.2 Layout....................................................................... 13
10 Device and Documentation Support..........................14
10.1 Documentation Support (Analog)............................14
10.2 接收文档更新通知................................................... 14
10.3 支持资源..................................................................14
10.4 Trademarks............................................................. 14
10.5 静电放电警告.......................................................... 14
10.6 术语表..................................................................... 14
11 Revision History.......................................................... 14
12 Mechanical, Packaging, and Orderable
Information.................................................................... 15
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4 Related Products
DEVICE
PACKAGE
DESCRIPTION
SN74LV1T00
DCK, DBV
2-Input Positive-NAND Gate
SN74LV1T02
DCK, DBV
2-Input Positive-NOR Gate
SN74LV1T04
DCK, DBV
Inverter Gate
SN74LV1T08
DCK, DBV
2-Input Positive-AND Gate
SN74LV1T17
DCK, DBV
Single Schmitt-Trigger Buffer Gate
SN74LV1T14
DCK, DBV
Single Schmitt-Trigger Inverter Gate
SN74LV1T32
DCK, DBV
2-Input Positive-OR Gate
SN74LV1T34
DCK, DBV
Single Buffer Gate
SN74LV1T86
DCK, DBV
Single 2-Input Exclusive-Or Gate
SN74LV1T125
DCK, DBV
Single Buffer Gate with 3-state Output
SN74LV1T126
DCK, DBV
Single Buffer Gate with 3-state Output
SN74LV4T125
RGY, PW
Quadruple Bus Buffer Gate With 3-State Outputs
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5 Pin Configuration and Functions
N.C.
1
A
2
GND
3
5
VCC
4
Y
图 5-1. DCK or DBV Package, 5-Pin SC70 or SOT-23 (Top View)
表 5-1. Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NC
1
—
A
2
I
Input A
GND
3
G
Ground
Y
4
O
Output Y
VCC
5
P
Positive supply
(1)
4
NO.
Not internally connected
I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage range
VI
Input voltage
range(2)
VO
Voltage range applied to any output in the high or low
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0 or VO > VCC
IO
Continuous output current
state(2)
MIN
MAX
–0.5
7.0
UNIT
V
–0.5
7.0
V
–0.5
VCC + 0.5
V
–20
mA
±20
mA
±25
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
(1)
(2)
Electrostatic discharge
UNIT
±2000
Machine Model (MM), per JEDEC specification
±200
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
Δt/Δv
TA
(1)
Input transition rise or fall rate
MIN
MAX
1.6
5.5
V
0
5.5
V
0
VCC
V
VCC = 1.8 V
–3
VCC = 2.5 V
–5
VCC = 3.3 V
–7
VCC = 5.0 V
–8
VCC = 1.8 V
3
VCC = 2.5 V
5
VCC = 3.3 V
7
VCC = 5.0 V
8
VCC = 1.8 V
20
VCC = 3.3 V or 2.5 V
20
VCC = 5.0 V
20
Operating free-air temperature
–40
125
UNIT
mA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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6.4 Thermal Information
THERMAL METRIC(1)
RθJA
(1)
Junction-to-ambient thermal resistance
DBV
DCK
5 PINS
5 PINS
278
289.2
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
VIL
TEST CONDITIONS
High-level
input voltage
Low-level
input voltage
VCC
TA = 25°C
MIN
TYP
IOH = –2.0 mA
VOH
High-level
output
voltage
0.95
1
VCC = 2.0 V
0.99
1.03
VCC = 2.25 V to 2.5 V
1.145
1.18
VCC = 2.75 V
1.22
1.25
VCC = 3 V to 3.3 V
1.37
1.39
VCC = 3.6 V
1.47
1.48
VCC = 4.5 V to 5.0 V
2.02
2.03
VCC = 5.5 V
2.1
0.55
0.75
0.71
VCC = 3 V to 3.6 V
0.8
0.65
6
1.21
1.93
2.5 V
2.25
2.15
3.3 V
4.5 V
5.0 V
2.78
2.7
2.6
2.49
2.9
2.8
4.2
4.1
4.1
3.95
4.6
4.5
V
IOL = 20 µA
1.65 V to 5.5 V
0.1
0.1
IOL = 2.0 mA
1.65 V
0.2
0.25
IOL = 3.0 mA
2.3 V
0.15
0.2
0.11
0.15
0.21
0.252
IOL = 3.0 mA
IOL = 5.5 mA
IOL = 8.0 mA
ICC
1.28
IOH = –3.0 mA
IOL = 4.0 mA
Input
leakage
current
1.65 V
3.0 V
A input; VI = 0 V or VCC
Static supply VI = 0 V or VCC,
current
IO = 0; open on loading
3.0 V
0.15
0.2
0.3
0.35
0.1
±1
5.0 V
1
10
3.3 V
1
10
2.5 V
1
10
1.8 V
1
10
4.5 V
0 V, 1.8 V, 2.5 V,
3.3 V, 5.5 V
V
0.8
VCC – 0.1
1.45
IOH = –8.0 mA
II
0.8
VCC – 0.1
2
IOH = –8.0 mA
V
VCC = 2.25 V to 2.75 V
1.65 V to 5.5 V
UNIT
2.11
1.5
IOH = –5.5 mA
MAX
0.57
2.3 V
IOH = –3.0 mA
TYP
VCC = 1.65 V to 2.0 V
1.8 V
IOH = –4.0 mA
Low-level
output
voltage
MIN
IOH = –3.0 mA
IOH = –5.5 mA
VOL
MAX
VCC = 1.65 V to 1.8 V
VCC = 4.5 V to 5.5 V
IOH = –20 µA
TA = –40°C to +125°C
V
μA
μA
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over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
ΔICC
TEST CONDITIONS
One input at 0.3 V or 3.4 V,
Other inputs at 0 or VCC,
IO = 0
Additional
static supply
One input at 0.3 V or 1.1 V
current
Other inputs at 0 or VCC,
IO = 0
TA = 25°C
VCC
MIN
TA = –40°C to +125°C
TYP
MAX
MIN
TYP
MAX
UNIT
5.5 V
1.35
1.5
mA
1.8 V
10
10
μA
10
pF
Ci
Input
VI = VCC or GND
capacitance
3.3 V
2
Co
Output
VO = VCC or GND
capacitance
3.3 V
2.5
10
2
2.5
pF
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Load Circuit and Voltage Waveforms)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
FREQUENCY
(TYP)
VCC
5.0 V
DC to 50 MHz
3.3 V
tpd
Any In
Y
DC to 25 MHz
2.5 V
DC to 15 MHz
1.8 V
CL
TA = 25°C
MIN
TA = –65°C to 125°C
TYP
MAX
15 pF
2.7
30 pF
MIN
TYP
MAX
5.5
3.4
6.5
3
6.5
4.1
7.5
15 pF
4
7
5
8
30 pF
4.9
8
6
9
15 pF
5.8
8.5
6.8
9.5
30 pF
6.5
9.5
7.5
10.5
15 pF
10.5
13
11.8
14
30 pF
12
14.5
12
15.5
UNIT
ns
ns
ns
ns
6.7 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 1 MHz and 10 MHz
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VCC
TYP
1.8 V ± 0.15 V
14
2.5 V ± 0.2 V
14
3.3 V ± 0.3 V
14
5.5 V ± 0.5 V
14
UNIT
pF
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6.8 Typical Characteristics
3.5
3.5
Output
Input
3
2.5
2.5
2
2
Voltage (V)
Voltage (V)
3
1.5
1
1.5
1
0.5
0.5
0
0
Output
Input
-0.5
-0.5
0
5
10
Time (ns)
15
0
20
2
4
6
8
D001
图 6-1. Switching Characteristics at 50 MHz Excellent Signal
Integrity
10
12
Time (ns)
14
16
18
20
D002
图 6-2. Switching Characteristics at 50 MHz Excellent Signal
Integrity
3.5
Output
Input
3
Voltage (V)
2.5
2
1.5
1
0.5
0
-0.5
0
12.5
25
37.5
50
Time (ns)
62.5
75
87.5
D003
图 6-3. Switching Characteristics at 15 MHz Excellent Signal Integrity
8
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7 Parameter Measurement Information
Test
Point
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
1.5 V
1.5 V
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
3V
Output
Control
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
图 7-1. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LV1T34 device is a low-voltage CMOS gate logic that operates at a wider voltage range for industrial,
portable, telecom, and automotive applications. The output level is referenced to the supply voltage and is able
to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to
match 1.8 V input logic at VCC = 3.3 V and can be used in 1.8 V to 3.3 V level-up translation. In addition, the 5 V
tolerant input pins enable down translation (that is, 3.3 V to 2.5 V output at VCC = 2.5 V). The wide VCC range of
1.8 V to 5.5 V allows generation of desired output levels to connect to controllers or processors. The
SN74LV1T34 device is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and
undershoot caused by high-drive outputs.
8.2 Functional Block Diagram
2
4
A
Y
图 8-1. Logic Diagram
8.3 Feature Description
8.3.1 Clamp Diode Structure
The outputs to this device have both positive and negative clamping diodes, and the inputs to this device have
negative clamping diodes only as depicted in 图 8-2.
小心
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
Device
VCC
+IOK
Input
Output
Logic
-IIK
-IOK
GND
图 8-2. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.2 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
10
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8.3.3 LVxT Enhanced Input Voltage
The SN74LV1T34 belongs to TI's LVxT family of Logic devices with integrated voltage level translation. This
family of devices was designed with reduced input voltage thresholds to support up-translation, and inputs
tolerant of signals with up to 5.5 V levels to support down-translation. The output voltage will always be
referenced to the supply voltage (VCC), as described in the Electrical Characteristics table. To ensure proper
functionality, input signals must remain at or below the specified VIH(MIN) level for a HIGH input state, and at or
below the specified VIL(MAX) for a LOW input state. 图 8-3 shows the typical VIH and VIL levels for the LVxT family
of devices, as well as the voltage levels for standard CMOS devices for comparison.
The inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance
given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage,
given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical
Characteristics, using Ohm's law (R = V ÷ I).
The inputs require that input signals transition between valid logic states quickly, as defined by the input
transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification will
result in excessive power consumption and could cause oscillations. More details can be found in the
Implications of Slow or Floating CMOS Inputs application report.
Do not leave inputs floating at any time during operation. Unused inputs must be terminated at VCC or GND. If a
system will not be actively driving an input at all times, a pull-up or pull-down resistor can be added to provide a
valid input voltage during these times. The resistor value will depend on multiple factors; however, a 10-kΩ
resistor is recommended and will typically meet all requirements.
3.6
3.4
3.3-V CMOS
3.2
VIH
3
VIL
HIGH Input
2.8
LOW Input
2.6
2.5-V CMOS
2.4
2.4 V (VOH)
VIN - Input Voltage (V)
2.2
2
2 V (VOH)
1.8-V CMOS
1.8
1.6
1.45 V (VOH)
1.4
1.2
1.2-V CMOS
1.1 V (VOH)
1
0.8
0.6
0.45 V (VOL)
0.4
0.4 V (VOL)
0.4 V (VOL)
0.3 V (VOL)
0.2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
5
5.2
5.5
VCC - Supply Voltage (V)
图 8-3. LVxT Input Voltage Levels
8.3.3.1 Down Translation
Signals can be translated down using the SN74LV1T34. The voltage applied at the VCC will determine the output
voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical
Characteristics tables.
When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and
0 V in the LOW state. Ensure that the input signals in the HIGH state are between VIH(MIN) and 5.5 V, and input
signals in the LOW state are lower than VIL(MAX) as shown in 图 8-3.
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For example, standard CMOS inputs for devices operating at 5.0 V, 3.3 V or 2.5 V can be down-translated to
match 1.8 V CMOS signals when operating from 1.8-V VCC. See 图 8-4.
Down Translation Combinations:
• 1.8-V VCC – Inputs from 2.5 V, 3.3 V, and 5.0 V
• 2.5-V VCC – Inputs from 3.3 V and 5.0 V
• 3.3-V VCC – Inputs from 5.0 V
8.3.3.2 Up Translation
Input signals can be up translated using the SN74LV1T34. The voltage applied at VCC will determine the output
voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical
Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately VCC
in the HIGH state, and 0 V in the LOW state.
The inputs have reduced thresholds that allow for input high-state levels which are much lower than standard
values. For example, standard CMOS inputs for a device operating at a 5-V supply will have a VIH(MIN) of 3.5 V.
For the SN74LV1T34, VIH(MIN) with a 5-V supply is only 2 V, which would allow for up-translation from a typical
2.5-V to 5-V signals.
Ensure that the input signals in the HIGH state are above VIH(MIN) and input signals in the LOW state are lower
than VIL(MAX) as shown in 图 8-4.
Up Translation Combinations:
• 1.8-V VCC – Inputs from 1.2 V
• 2.5-V VCC – Inputs from 1.8 V
• 3.3-V VCC – Inputs from 1.8 V and 2.5 V
• 5.0-V VCC – Inputs from 2.5 V and 3.3 V
VIH = 2.0 V
VIL = 0.8 V
5.0 V
3.3 V
System
VIH = 0.99 V
VIL = 0.5 V
Vcc = 5.0 V
5.0 V
System
LV1Txx Logic
5.0 V, 3.3 V
2.5 V, 1.8 V
1.5 V, 1.2 V
System
Vcc = 1.8 V
LV1Txx Logic
1.8 V
System
图 8-4. LVxT Up and Down Translation Example
8.4 Device Functional Modes
表 8-1 is the function table for the SN74LV1T34.
表 8-1. Function Table
INPUT
(LOWER LEVEL INPUT)
12
OUTPUT
(VCC CMOS)
A
Y
H
H
L
L
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the
following layout example.
9.2 Layout
9.2.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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10 Device and Documentation Support
10.1 Documentation Support (Analog)
10.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application note
• Texas Instruments, Designing With Logic application note
• Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
application note
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击通知 进行注册，即可每周接收产品信息更改摘
要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索
现有解答或提出自己的问题，获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的使用条款。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (November 2023) to Revision E (February 2024)
Page
• Updated RθJA values: DBV = 206 to 278, all values in °C/W ......................................................................... 6
Changes from Revision C (June 2017) to Revision D (November 2023)
Page
• 向封装信息 表中添加了封装尺寸........................................................................................................................ 1
• Added Application and Implementation section................................................................................................13
14
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SN74LV1T34
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ZHCSBY2E – DECEMBER 2013 – REVISED FEBRUARY 2024
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN74LV1T34
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2025
PACKAGING INFORMATION
Orderable part number
(1)
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
SN74LV1T34DBVR
Active
Production
SOT-23 (DBV) | 5
3000 | LARGE T&R
Yes
SN
Level-1-260C-UNLIM
-40 to 125
(3B3H, 3CJF, NEJ3,
NEJJ, NEJS)
SN74LV1T34DBVR.A
Active
Production
SOT-23 (DBV) | 5
3000 | LARGE T&R
Yes
SN
Level-1-260C-UNLIM
-40 to 125
(3B3H, 3CJF, NEJ3,
NEJJ, NEJS)
SN74LV1T34DBVRG4
Active
Production
SOT-23 (DBV) | 5
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
NEJ3
SN74LV1T34DBVRG4.A
Active
Production
SOT-23 (DBV) | 5
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
NEJ3
SN74LV1T34DCKR
Active
Production
SC70 (DCK) | 5
3000 | LARGE T&R
Yes
SN
Level-1-260C-UNLIM
-40 to 125
(1R4, WJ3, WJJ, WJ
S)
SN74LV1T34DCKR.A
Active
Production
SC70 (DCK) | 5
3000 | LARGE T&R
Yes
SN
Level-1-260C-UNLIM
-40 to 125
(1R4, WJ3, WJJ, WJ
S)
SN74LV1T34DCKRG4
Active
Production
SC70 (DCK) | 5
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
WJ3
SN74LV1T34DCKRG4.A
Active
Production
SC70 (DCK) | 5
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
WJ3
Status: For more details on status, see our product life cycle.
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2025
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV1T34 :
• Automotive : SN74LV1T34-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2025
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SN74LV1T34DBVR
SOT-23
SN74LV1T34DBVRG4
SN74LV1T34DCKR
SN74LV1T34DCKRG4
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-23
DBV
5
3000
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
SC70
DCK
5
3000
180.0
8.4
2.3
2.5
1.2
4.0
8.0
Q3
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2025
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV1T34DBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
SN74LV1T34DBVRG4
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74LV1T34DCKR
SC70
DCK
5
3000
210.0
185.0
35.0
SN74LV1T34DCKRG4
SC70
DCK
5
3000
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
SCALE 5.600
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
1.4
1.1
PIN 1
INDEX AREA
B
1.1 MAX
A
5
1
NOTE 4
2X 0.65
1.3
0.1 C
(0.15)
2
1.3
2.15
1.85
(0.1)
0.33
0.15
C A B
4
3
5X
0.1
4X 0 -12
NOTE 5
(0.9)
0.1
TYP
0.0
4X 4 -15
0.15
0.22
TYP
0.08
GAGE PLANE
8
TYP
0
0.46
TYP
0.26
SEATING PLANE
4214834/G 11/2024
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
5. Lead width does not comply with JEDEC.
6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.25mm per side
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
5X (0.95)
PKG
1
5
5X (0.4)
SYMM
(1.3)
2
2X (0.65)
3
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214834/G 11/2024
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
2X(0.65)
4
3
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/G 11/2024
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
A
5
(0.1)
2X 0.95
1.9
0.1 C
B
3.05
2.75
1.9
2
(0.15)
4
0.5
5X
0.3
0.2
3
C A B
NOTE 5
4X 0 -15
(1.1)
0.15
TYP
0.00
1.45
0.90
4X 4 -15
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/K 08/2024
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/K 08/2024
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/K 08/2024
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPORTANT NOTICE
版权所有 © 2025，德州仪器 (TI) 公司
最后更新日期：2025 年 10 月
