SN74LV1T34DBVR

Order Now Product Folder Support & Community Tools & Software Technical Documents SN74LV1T34 SCLS743B – DECEMBER 2013 – REVISED JUNE 2017 SN74LV1T34 Single Power Supply Single Buffer GATE CMOS Logic Level Shifter 1 Features 2 Applications • • • • • • 1 • • • • • • • • • • • • (1) Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Single-Supply Voltage Translator at 5-V, 3.3-V, 2.5-V, and 1.8-V VCC Operating Range of 1.65 V to 5.5 V Up Translation – 1.2 V(1) to 1.8 V at 1.8-V VCC – 1.5 V(1) to 2.5 V at 2.5-V VCC – 1.8 V(1) to 3.3 V at 3.3-V VCC – 3.3 V to 5.0 V at 5.0-V VCC Down Translation – 3.3 V to 1.8 V at 1.8-V VCC – 3.3 V to 2.5 V at 2.5-V VCC – 5 V to 3.3 V at 3.3-V VCC Logic Output is Referenced to VCC Output Drive – 8 mA Output Drive at 5.0 V – 7 mA Output Drive at 3.3 V – 3 mA Output Drive at 1.8 V Characterized up to 50 MHz at 3.3 V VCC 5-V Tolerance on Input Pins –40°C to +125°C Operating Temperature Range Supports Standard Logic Pinouts CMOS Output Backward Compatible With AUP1G and LVC1G Families Industrial Controllers Telecom Portable Applications Servers PC and Notebooks 3 Description The SN74LV1T34 device is a low voltage CMOS gate logic that operates at a wider voltage range for industrial, portable, and telecom applications. The output level is referenced to the supply voltage and is able to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to match 1.8 V input logic at VCC = 3.3 V and can be used in 1.8 V to 3.3 V level up translation. In addition, the 5 V tolerant input pins enable down translation (that is, 3.3 V to 2.5 V output at VCC = 2.5 V). The wide VCC range of 1.8 V to 5.5 V allows generation of desired output levels to connect to controllers or processors. The SN74LV1T34 device is designed with currentdrive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74LV1T34DBV SOT-23 (5) 2.90 mm x 1.60 mm SN74LV1T34DCK SC70 (5) 2.00 mm x 1.25 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Refer to the VIH/VIL and output drive for lower VCC condition Logic Diagram 2 A 4 Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LV1T34 SCLS743B – DECEMBER 2013 – REVISED JUNE 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 3 3 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Operating Characteristics.......................................... Typical Characteristics .............................................. 7 8 Parameter Measurement Information .................. 8 Detailed Description .............................................. 9 8.1 Functional Block Diagram ......................................... 9 8.2 Device Functional Modes.......................................... 9 9 Device and Documentation Support.................. 10 9.1 9.2 9.3 9.4 9.5 9.6 9.7 Device Support........................................................ 10 Documentation Support .......................................... 10 Receiving Notification of Documentation Updates.. 10 Community Resources............................................ 10 Trademarks ............................................................. 10 Electrostatic Discharge Caution .............................. 10 Glossary .................................................................. 10 10 Mechanical, Packaging, and Orderable Information ........................................................... 11 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2014) to Revision B Page • Deleted DPW Package throughout data sheet....................................................................................................................... 1 • Added Pin Configuration and Functions section, ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Device Support, Documentation Support, Receiving Notification of Documentation Updates, and Community Resources............................................................................................................ 1 • Added Typical Characteristics ................................................................................................................................................ 7 • Deleted function table for the Supply Vcc = 3.3 V test case .................................................................................................. 9 Changes from Original (December 2013) to Revision A • 2 Page Updated document formatting. ............................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: SN74LV1T34 SN74LV1T34 www.ti.com SCLS743B – DECEMBER 2013 – REVISED JUNE 2017 5 Pin Configuration and Functions DBV or DCK Package 5-Pin SOT-23 or SC70 Top View N.C. 1 A 2 GND 3 5 VCC 4 Y Pin Functions PIN NAME NO. I/O DESCRIPTION A 2 I Input A GND 3 — Ground N.C. 1 — No Connect VCC 5 — Power Supply Y 4 O Output Y 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX UNIT Supply voltage –0.5 7 V (2) –0.5 7 V –0.5 VCC + 0.5 V VI Input voltage VO Voltage range applied to any output in the high or low state (2) IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current ±25 mA Continuous current through VCC or GND ±50 mA 150 °C 150 °C Tstg Storage temperature TJ Junction temperature (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged device model (CDM), per JEDEC specification JESD22-C101 (2) 1000 Machine Model (A115-A) 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: SN74LV1T34 3 SN74LV1T34 SCLS743B – DECEMBER 2013 – REVISED JUNE 2017 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Supply voltage 1.6 5.5 V VI Input voltage 0 5.5 V VO Output voltage 0 VCC V IOH High-level output current IOL Low-level output current Δt/Δv TA (1) Input transition rise or fall rate VCC = 1.8 V –3 VCC = 2.5 V –5 VCC = 3.3 V –7 VCC = 5 V –8 VCC = 1.8 V 3 VCC = 2.5 V 5 VCC = 3.3 V 7 VCC = 5 V 8 VCC = 1.8 V 20 VCC = 3.3 V or 2.5 V 20 VCC = 5 V 20 Operating free-air temperature –40 mA mA ns/V 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating CMOS Inputs, SCBA004. 6.4 Thermal Information THERMAL METRIC (1) RθJA (1) Junction-to-ambient thermal resistance DBV DCK 5 PINS 5 PINS 206 252 UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIH VIL 4 High-level input voltage Low-level input voltage TA = –40°C to +125°C TA = 25°C VCC TYP MAX MIN VCC = 1.65 V to 1.8 V 0.95 1 VCC = 2 V 0.99 1.03 VCC = 2.25 V to 2.5 V 1.145 1.18 VCC = 2.75 V 1.22 1.25 1.37 1.39 VCC = 3 V to 3.3 V VCC = 3.6 V 1.47 1.48 VCC = 4.5 V to 5 V 2.02 2.03 VCC = 5.5 V 2.1 UNIT MAX V 2.11 VCC = 1.65 V to 2 V 0.57 0.55 VCC = 2.25 V to 2.75 V 0.75 0.71 VCC = 3 V to 3.6 V 0.8 0.65 VCC = 4.5 V to 5.5 V 0.8 0.8 Submit Documentation Feedback V Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: SN74LV1T34 SN74LV1T34 www.ti.com SCLS743B – DECEMBER 2013 – REVISED JUNE 2017 Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN IOH = –20 µA 1.65 V to 5.5 V VCC – 0.1 1.21 1.8 V 1.5 1.45 IOH = –3.0 mA 2.3 V 2 1.93 IOH = –3.0 mA 2.5 V 2.25 2.15 3V IOH = –5.5 mA 3.3 V IOH = –4.0 mA 4.5 V IOH = –8.0 mA IOH = –8.0 mA 5V 2.7 2.6 2.49 2.9 2.8 4.2 4.1 4.1 3.95 4.6 V V 4.5 1.65 V to 5.5 V 0.1 0.1 IOL = 2.0 mA 1.65 V 0.2 0.25 IOH = 3.0 mA 2.3 V 0.15 0.2 0.11 0.15 0.21 0.252 3V IOL = 5.5 mA IOL = 4.0 mA 4.5 V IOL = 8.0 mA 0 V, 1.8 V, 2.5 V, 3.3 V, 5.5 V VI = 0 V or VCC VI = 0 V or VCC; IO = 0; Open on loading ICC 2.78 UNIT MAX IOL = 20 µA IOL = 3.0 mA A input MIN 1.28 IOH = –5.5 mA II MAX VCC – 0.1 IOH = –3.0 mA VOL TYP 1.65 V IOH = –2.0 mA VOH TA = –40°C to +125°C TA = 25°C VCC 0.15 0.2 0.3 0.35 0.1 ±1 5V 1 10 3.3 V 1 10 2.5 V 1 10 V µA µA 1.8 V 1 10 One input at 0.3 V or 3.4 V Other inputs at 0 or VCC, IO = 0 5.5 V 1.35 1.5 mA One input at 0.3 V or 1.1 V Other inputs at 0 or VCC, IO = 0 1.8 V 10 10 µA Ci VI = VCC or GND 3.3 V 2 10 pF Co VO = VCC or GND 3.3 V 2.5 ΔICC 10 2 2.5 pF 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) FREQUENCY (TYP) VCC 5.0 V DC to 50 MHz 3.3 V tpd Any In Y DC to 25 MHz 2.5 V DC to 15 MHz 1.8 V CL TA = 25°C MIN TA = –65°C to 125°C TYP MAX 15 pF 2.7 30 pF 3 15 pF 30 pF 15 pF 30 pF 15 pF 30 pF MIN TYP MAX 5.5 3.4 6.5 6.5 4.1 7.5 4 7 5 8 4.9 8 6 9 5.8 8.5 6.8 9.5 6.5 9.5 7.5 10.5 10.5 13 11.8 14 12 14.5 12 15.5 UNIT Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: SN74LV1T34 ns ns ns ns 5 SN74LV1T34 SCLS743B – DECEMBER 2013 – REVISED JUNE 2017 www.ti.com 6.7 Operating Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance VIH = 2.0V VIL = 0.8V 5.0V 3.3V System f = 1 MHz and 10 MHz VIH = 0.99V VIL = 0.55V Vcc = 5.0V LV1Txx Logic 5.0V, 3.3V 2.5V, 1.8V 1.5V, 1.2V System 5.0V System VCC TYP 1.8 V ± 0.15 V 14 2.5 V ± 0.2 V 14 3.3 V ± 0.3 V 14 5 V ± 0.5 V 14 UNIT pF Vcc = 1.8V LV1Txx Logic 1.8V System Vcc = 3.3V 5.0V, 3.3V 2.5V, 1.8V System LV1Txx Logic 3.3V System VOH min = 2.4V VIH min = 1.36V VOL max = 0.4V VIL min = 0.8V Figure 1. Switching Thresholds For 1.8-V to 3.3-V Translation 6 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: SN74LV1T34 SN74LV1T34 www.ti.com SCLS743B – DECEMBER 2013 – REVISED JUNE 2017 6.8 Typical Characteristics 3.5 3.5 Output Input 3 2.5 2.5 2 2 Voltage (V) Voltage (V) 3 1.5 1 1.5 1 0.5 0.5 0 0 -0.5 Output Input -0.5 0 5 10 Time (ns) 15 20 0 2 4 6 8 D001 10 12 Time (ns) 14 16 18 1.8 V to 3.3 V at 3.3-V VCC 3.3 V to 3.3 V at 3.3-V VCC Figure 2. Switching Characteristics at 50 MHz Excellent Signal Integrity Figure 3. Switching Characteristics at 50 MHz Excellent Signal Integrity 20 D002 3.5 Output Input 3 Voltage (V) 2.5 2 1.5 1 0.5 0 -0.5 0 12.5 25 37.5 50 Time (ns) 62.5 75 87.5 D003 3.3 V to 1.8 V at 1.8-V VCC Figure 4. Switching Characteristics at 15 MHz Excellent Signal Integrity Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: SN74LV1T34 7 SN74LV1T34 SCLS743B – DECEMBER 2013 – REVISED JUNE 2017 www.ti.com 7 Parameter Measurement Information Test Point From Output Under Test RL = 1 kΩ From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL 1.5 V tPLZ tPZL ≈VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V VOL + 0.3 V VOL tPHZ tPZH tPLH 50% VCC 3V Output Control 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 5. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: SN74LV1T34 SN74LV1T34 www.ti.com SCLS743B – DECEMBER 2013 – REVISED JUNE 2017 8 Detailed Description 8.1 Functional Block Diagram 2 4 A Y Figure 6. Logic Diagram 8.2 Device Functional Modes Table 1 is the function table for the SN74LV1T34. Table 1. Function Table INPUT (LOWER LEVEL INPUT) OUTPUT (VCC CMOS) A Y H H L L Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: SN74LV1T34 9 SN74LV1T34 SCLS743B – DECEMBER 2013 – REVISED JUNE 2017 www.ti.com 9 Device and Documentation Support 9.1 Device Support Table 2. Additional Product Selection DEVICE PACKAGE DESCRIPTION SN74LV1T00 DCK, DBV 2-Input Positive-NAND Gate SN74LV1T02 DCK, DBV 2-Input Positive-NOR Gate SN74LV1T04 DCK, DBV Inverter Gate SN74LV1T08 DCK, DBV 2-Input Positive-AND Gate SN74LV1T34 DCK, DBV Single Buffer Gate SN74LV1T14 DCK, DBV Single Schmitt-Trigger Inverter Gate SN74LV1T32 DCK, DBV 2-Input Positive-OR Gate SN74LV1T86 DCK, DBV Single 2-Input Exclusive-Or Gate SN74LV1T125 DCK, DBV Single Buffer Gate with 3-State Output SN74LV1T126 DCK, DBV Single Buffer Gate with 3-State Output SN74LV4T125 RGY, PW Quadruple Bus Buffer Gate With 3-State Outputs 9.2 Documentation Support 9.2.1 Related Documentation For related documentation see the following: Implications of Slow or Floating CMOS Inputs, SCBA004. 9.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 9.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 9.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 9.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 9.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 10 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: SN74LV1T34 SN74LV1T34 www.ti.com SCLS743B – DECEMBER 2013 – REVISED JUNE 2017 10 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: SN74LV1T34 11 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74LV1T34DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (NEJ3, NEJJ, NEJS) SN74LV1T34DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 NEJ3 SN74LV1T34DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (WJ3, WJJ, WJS) SN74LV1T34DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM WJ3 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of