SN74LV32AMPWREP

SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 FEATURES • • • • • • • • • (1) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) 2-V to 5.5-V VCC Operation Max tpd of 7.5 ns at 5 V Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • • Supports Mixed-Mode Voltage Operation on All Ports Ioff Supports Partial-Power-Down Mode Operation PW PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. DESCRIPTION/ORDERING INFORMATION This quadruple 2-input positive-OR gate is designed for 2-V to 5.5-V VCC operation The SN74LV32A-EP performs the Boolean function Y + A ) B or Y + A • B in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE (1) TA ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 105°C TSSOP – PW Tape and reel SN74LV32ATPWREP LV32AEP –55°C to 125°C TSSOP – PW Tape and reel SN74LV32AMPWREP LV32AEP (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (EACH GATE) INPUTS A B OUTPUT Y H X H X H H L L L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2006, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC) A Y B Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 7 UNIT V range (2) VI Input voltage –0.5 7 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 7 V VO Output voltage range (2) (3) –0.5 VCC + 0.5 IIK Input clamp current IOK IO –20 mA Output clamp current VO < 0 –50 mA Continuous output current VO = 0 to VCC ±25 mA ±50 mA 113 °C/W 150 °C Continuous current through VCC or GND impedance (4) θJA Package thermal Tstg Storage temperature range (1) (2) (3) (4) 2 V VI < 0 –65 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com Recommended Operating Conditions SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 (1) Supply voltage VCC VCC = 2 V High-level input voltage VIH MIN MAX 2 5.5 Low-level input voltage VI Input voltage VO Output voltage VCC = 2.3 V to 2.7 V VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC = 2.3 V to 2.7 V VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3 5.5 0 VCC V –50 μA VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V –6 Δt/Δv Input transition rise or fall rate 50 VCC = 2.3 V to 2.7 V 2 VCC = 3 V to 3.6 V 6 VCC = 4.5 V to 5.5 V 12 VCC = 2.3 V to 2.7 V 200 VCC = 3 V to 3.6 V 100 VCC = 4.5 V to 5.5 V TA (1) Operating free-air temperature mA –12 VCC = 2 V Low-level output current V –2 VCC = 4.5 V to 5.5 V IOL V 0 VCC = 2 V High-level output current V 0.5 VCC = 4.5 V to 5.5 V IOH V 1.5 VCC = 2 V VIL UNIT μA mA ns/V 20 SN74LV32AM –55 125 SN74LV32AT –40 105 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS VCC 2 V to 5.5 V IOH = –2 mA 2.3 V IOH = –6 mA 3V 2.48 4.5 V 3.8 IOH = –12 mA VOL TYP MAX 2 V to 5.5 V V 0.1 IOL = 2 mA 2.3 V 0.4 IOL = 6 mA 3V 0.44 IOL = 12 mA 4.5 V 0.55 II VI = 5.5 V or GND VI = VCC or GND, Ioff VI or VO = 0 to 5.5 V UNIT VCC – 0.1 2 IOL = 50 μA ICC Ci MIN IOH = –50 μA V 0 to 5.5 V ±1 μA 5.5 V 20 μA 5 μA IO = 0 0 VI = VCC or GND 3.3 V 3.3 5V 3.3 pF Switching Characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tpd A or B Y CL = 50 pF TA = 25°C MIN TYP MAX 9.6 16.2 MIN MAX 1 20 UNIT ns Switching Characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tpd A or B Y CL = 50 pF TA = 25°C MIN TYP MAX 6.9 11.4 MIN MAX 1 13 UNIT ns Switching Characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) 4 PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tpd A or B Y CL = 50 pF TA = 25°C MIN TYP MAX 4.9 7.5 MIN MAX 1 8.5 UNIT ns SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com Noise Characteristics SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 (1) VCC = 3.3 V, CL = 50 pF, TA = 25°C TYP MAX VOL(P) Quiet output, maximum dynamic VOL MIN 0.2 0.8 V VOL(V) Quiet output, minimum dynamic VOL –0.1 –0.8 V VOH(V) Quiet output, minimum dynamic VOH VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) 3.1 UNIT V 2.31 V 0.99 V TYP UNIT Characteristics are for surface-mount packages only. Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 10 MHz VCC 3.3 V 9.5 5V 11.5 pF 5 SN74LV32A-EP QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCLS565B – JANUARY 2004 – REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) VCC S1 Open TEST GND CL (see Note A) LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 0V 50% VCC 50% VCC 0V Data Input VCC 0V tPHL Out-of-Phase Output 0V VOH 50% VCC VOL VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC tPZL tPLH 50% VCC VCC Output Control tPHL 50% VCC 50% VCC VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 50% VCC tPLH VCC 50% VCC VOLTAGE WAVEFORMS PULSE DURATION 50% VCC th tsu VCC In-Phase Output VCC 50% VCC tw Input Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS Timing Input Input S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Output Waveform 1 S1 at VCC (see Note B) 0V tPLZ 50% VCC ≈VCC VOL + 0.3 V VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) 50% VCC 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuits and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LV32AMPWREP ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 LV32AEP SN74LV32ATPWREP ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LV32AEP V62/04693-01XE ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LV32AEP V62/04693-02XE ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 LV32AEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of