SN74LV541AT
www.ti.com
SCES573B – JUNE 2004 – REVISED JULY 2013
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
Check for Samples: SN74LV541AT
FEATURES
DESCRIPTION
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The SN74LV541AT is designed for 4.5-V to 5.5-V
VCC operation. The inputs are TTL-voltage
compatible, which allows them to be interfaced with
bipolar outputs and 3.3-V devices. The device also
can be used to translate from 3.3 V to 5 V.
1
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Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V VCC Operation
Typical tpd of 4 ns at 5 V
Typical VOLP (Output Ground Bounce)
2.3 V at VCC = 5 V, TA = 25°C
Supports Mixed-Mode Voltage Operation on
All Ports
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
This device is ideal for driving bus lines or buffer
memory address registers. It features inputs and
outputs on opposite sides of the package to facilitate
printed circuit board layout.
The 3-state control gate is a two-input AND gate with
active-low inputs so that, if either output-enable (OE1
or OE2) input is high, all corresponding outputs are in
the high-impedance state. The outputs provide
noninverted data when they are not in the highimpedance state.
To ensure the high-impedance state during power up
or power down, OE shall be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1
A2
A3
A4
A5
A6
A7
A8
VCC
19
1
20
3
4
19 OE2
18 Y1
17 Y2
5
6
16 Y3
15 Y4
7
8
14 Y5
13 Y6
2
12 Y7
9
10
11
Y8
20
2
OE1
1
GND
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
RGY PACKAGE
(TOP VIEW)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
SN74LV541AT
SCES573B – JUNE 2004 – REVISED JULY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTION TABLE
(EACH BUFFER/DRIVER)
INPUTS
OUTPUT
Y
OE1
OE2
A
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
OE1
OE2
A1
1
19
2
18
Y1
To Seven Other Channels
2
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Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: SN74LV541AT
SN74LV541AT
www.ti.com
SCES573B – JUNE 2004 – REVISED JULY 2013
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
7
V
VI
Input voltage range (2)
–0.5
7
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage range applied in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
±70
mA
Continuous current through VCC or GND
θJA
Package thermal impedance
Tstg
(1)
(2)
(3)
(4)
(5)
DB package (4)
70
DGV package (4)
92
DW package
(4)
58
NS package (4)
60
PW package (4)
83
RGY package (5)
37
Storage temperature range
–65
150
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7
The package thermal impedance is calculated in accordance with JESD 51-5.
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
VI
Input voltage
MIN
MAX
4.5
5.5
2
UNIT
V
V
0.8
V
V
0
5.5
High or low state
0
VCC
3-state
0
5.5
VO
Output voltage
IOH
High-level output current
VCC = 4.5 V to 5.5 V
–16
IOL
Low-level output current
VCC = 4.5 V to 5.5 V
16
mA
Δt/Δv
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V
20
ns/V
TA
Operating free-air temperature
125
°C
(1)
–40
V
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74LV541AT
SCES573B – JUNE 2004 – REVISED JULY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMET
ER
TEST CONDITIONS
VOH
VOL
TA = –40°C to 85°C
SN74LV541AT
SN74LV541AT
MIN
TYP
IOH = –50 μA
4.5 V
4.4
4.5
IOH = –16 mA
4.5 V
3.8
IOL = 50 μA
4.5 V
IOL = 16 mA
4.5 V
MAX
0
MIN
TA = –40°C to 125°C
Recommended
UNIT
SN74LV541AT
MAX
MIN
4.4
4.4
3.8
3.8
TYP
MAX
V
0.1
0.1
0.1
0.55
0.55
0.55
V
II
VI = 5.5 V or GND
0 to 5.5 V
±0.1
±1
±1
μA
IOZ
VO = VCC or GND
5.5 V
±0.25
±2.5
±2.5
μA
ICC
VI = VCC or GND, IO = 0
5.5 V
2
20
20
μA
One input at 3.4 V, Other inputs at VCC or
GND
5.5 V
1.35
1.5
150
mA
0.5
5
5
μA
ΔICC
(1)
VCC
TA = 25°C
(1)
Ioff
VI or VO = 0 to 5.5 V
Ci
VI = VCC or GND
0
2
pF
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
tpd
A
ten
OE
tdis
OE
Y
PARAMETER
TA = 25°C
LOAD
CAPACITANCE
TA = 25°C to
125°C
TA = –40°C to
85°C
UNIT
Recommended
MIN
TYP
MAX
MIN
MAX
2.6
5
6.9
1
8
1
9
3
8.3
11.3
1
13
1
14
1.4
3.9
7.5
1
8
1
8.5
Y
4
5.5
7.9
1
9
1
10
Y
3.8
8.8
12.3
1
14
1
15.2
2.1
9.4
11.9
1
13.5
1
14
CL = 15 pF
CL = 50 pF
tsk(o)
1
MIN TYP
MAX
ns
ns
1
NOISE CHARACTERISTICS (1)
VCC = 5 V, CL = 50 pF
TA = 25°C
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
1.1
1.5
V
VOL(V)
Quiet output, minimum dynamic VOL
–1.1
–1.5
V
VOH(V)
Quiet output, minimum dynamic VOH
4
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
V
2
V
0.8
V
Characteristics are for surface-mount packages only.
OPERATING CHARACTERISTICS
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
CL = 50 pF,
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f = 10 MHz
TYP
8
UNIT
pF
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: SN74LV541AT
SN74LV541AT
www.ti.com
SCES573B – JUNE 2004 – REVISED JULY 2013
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
Test
Point
RL = 1 kΩ
From Output
Under Test
CL
(see Note A)
S1
Open
TEST
GND
S1
Open
VCC
GND
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPHL
tPLH
VOH
In-Phase
Output
50% VCC
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
VOH
50% VCC
VOL
1.5 V
1.5 V
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
tPHL
Out-of-Phase
Output
50% VCC
VOL
3V
Output
Control
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuits and Voltage Waveforms
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Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: SN74LV541AT
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SN74LV541AT
SCES573B – JUNE 2004 – REVISED JULY 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (August 2005) to Revision B
•
6
Page
Added parameter values for –40 to 125°C temperature ratings. .......................................................................................... 4
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Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: SN74LV541AT
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LV541ATDBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541AT
SN74LV541ATDGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541AT
SN74LV541ATDW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541AT
SN74LV541ATDWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541AT
SN74LV541ATNSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV541AT
SN74LV541ATPW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541AT
SN74LV541ATPWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541AT
SN74LV541ATPWT
ACTIVE
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541AT
SN74LV541ATRGYR
ACTIVE
VQFN
RGY
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
VV541
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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