SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
D 2-V to 5.5-V VCC Operation
D Max tpd of 8.5 ns at 5 V
D Typical VOLP (Output Ground Bounce)
SN54LV74A . . . J OR W PACKAGE
SN74LV74A . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
2
13
3
12
4
11
5
10
6
9
7
8
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
1D
1CLK
1PRE
1Q
1Q
14
1D
1CLR
NC
VCC
2CLR
1
2
13 2CLR
3
12 2D
4
11 2CLK
5
10 2PRE
9 2Q
6
7
8
SN54LV74A . . . FK PACKAGE
(TOP VIEW)
1CLK
NC
1PRE
NC
1Q
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2D
NC
2CLK
NC
2PRE
1Q
GND
NC
2Q
2Q
14
VCC
1
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN74LV74A . . . RGY PACKAGE
(TOP VIEW)
2Q
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
D
1CLR
D
D
2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
GND
D
D Ioff Supports Partial-Power-Down Mode
NC − No internal connection
description/ordering information
These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCC operation.
ORDERING INFORMATION
PACKAGE†
TA
QFN − RGY
SN74LV74ARGYR
Tube of 50
SN74LV74AD
Reel of 2500
SN74LV74ADR
SOP − NS
Reel of 2000
SN74LV74ANSR
74LV74A
SSOP − DB
Reel of 2000
SN74LV74ADBR
LV74A
Tube of 90
SN74LV74APW
Reel of 2000
SN74LV74APWR
Reel of 250
SN74LV74APWT
TVSOP − DGV
Reel of 2000
SN74LV74ADGVR
LV74A
CDIP − J
Tube of 25
SNJ54LV74AJ
SNJ54LV74AJ
CFP − W
Tube of 150
SNJ54LV74AW
SNJ54LV74AW
LCCC − FK
Tube of 55
SNJ54LV74AFK
SNJ54LV74AFK
TSSOP − PW
−55°C
55 C to 125
125°C
C
†
TOP-SIDE
MARKING
Reel of 1000
SOIC − D
−40°C
40 C to 85°C
85 C
ORDERABLE
PART NUMBER
LV74A
LV74A
LV74A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
description/ordering information (continued)
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
†
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H†
H†
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic diagram, each flip-flop (positive logic)
PRE
CLK
C
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
C
C
C
Q
CLR
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV74A
VCC
MIN
MAX
2
5.5
Supply voltage
VCC = 2 V
VIH
High level input voltage
High-level
1.5
Low level input voltage
Low-level
VI
Input voltage
VO
Output voltage
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
VCC × 0.7
Input transition rise or fall rate
TA
Operating free-air temperature
V
V
0.5
0.5
VCC × 0.3
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC × 0.3
VCC × 0.3
5.5
0
5.5
0
VCC
0
VCC = 3 V to 3.6 V
VCC
V
−50
μA
−2
−2
−6
−6
−12
50
50
VCC = 2.3 V to 2.7 V
2
2
VCC = 3 V to 3.6 V
6
6
VCC = 4.5 V to 5.5 V
12
12
VCC = 2.3 V to 2.7 V
200
200
VCC = 3 V to 3.6 V
100
100
20
−55
V
−50
−12
VCC = 4.5 V to 5.5 V
V
VCC × 0.3
0
VCC = 2 V
Δt/Δv
UNIT
VCC = 2.3 V to 2.7 V
VCC = 2.3 V to 2.7 V
Low level output current
Low-level
5.5
VCC × 0.7
VCC = 4.5 V to 5.5 V
IOL
2
VCC = 2.3 V to 2.7 V
VCC = 2 V
High level output current
High-level
MAX
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
IOH
MIN
1.5
VCC = 2 V
VIL
SN74LV74A
125
mA
μA
mA
ns/V
20
−40
°C
85
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV74A
PARAMETER
VOH
TEST CONDITIONS
MIN
TYP
MIN
2 V to 5.5 V
IOH = −2 mA
2.3 V
2
2
IOH = −6 mA
3V
2.48
2.48
4.5 V
3.8
VCC−0.1
TYP
MAX
V
3.8
2 V to 5.5 V
0.1
0.1
IOL = 2 mA
2.3 V
0.4
0.4
IOL = 6 mA
3V
0.44
0.44
4.5 V
II
VI = 5.5 V or GND
ICC
VI = VCC or GND,
Ioff
VI or VO = 0 to 5.5 V
Ci
VI = VCC or GND
IO = 0
UNIT
VCC−0.1
IOL = 50 μA
IOL = 12 mA
V
0.55
0.55
0 to 5.5 V
±1
±1
μA
5.5 V
20
20
μA
0
5
5
μA
3.3 V
2
2
5V
2
2
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
SN74LV74A
MAX
IOH = −50 μA
IOH = −12 mA
VOL
VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
pF
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
PARAMETER
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
MIN
SN54LV74A
MAX
MIN
MAX
SN74LV74A
MIN
PRE or CLR low
8
9
9
CLK
8
9
9
Data
8
9
9
PRE or CLR inactive
7
7
7
0.5
0.5
0.5
MAX
UNIT
ns
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
PARAMETER
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
MIN
SN54LV74A
MAX
MIN
MAX
SN74LV74A
MIN
PRE or CLR low
6
7
7
CLK
6
7
7
Data
6
7
7
PRE or CLR inactive
5
5
5
0.5
0.5
0.5
MAX
UNIT
ns
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
PARAMETER
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
MIN
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
PRE or CLR
CLK
MAX
SN74LV74A
MIN
PRE or CLR low
5
5
5
5
5
5
Data
5
5
5
PRE or CLR inactive
3
3
3
0.5
0.5
0.5
free-air
TA = 25°C
SN54LV74A
TYP
CL = 15 pF
50*
100*
40*
40
CL = 50 pF
30
70
25
25
Q or Q
CL = 15 pF
Q or Q
CL = 50 pF
MIN
MAX
UNIT
ns
ns
ns
range,
SN74LV74A
MIN
MAX
MAX
temperature
LOAD
CAPACITANCE
PRE or CLR
tpd
MIN
CLK
switching characteristics over recommended operating
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
SN54LV74A
MAX
MIN
MAX
UNIT
MHz
9.8*
14.8*
1*
17*
1
17
11.1*
16.4*
1*
19*
1
19
13
17.4
1
20
1
20
14.2
20
1
23
1
23
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
switching characteristics over recommended operating
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
TA = 25°C
CLK
PRE or CLR
tpd
CLK
temperature
SN54LV74A
MIN
TYP
CL = 15 pF
80*
140*
70*
70
CL = 50 pF
50
90
45
45
Q or Q
CL = 15 pF
Q or Q
CL = 50 pF
MAX
MIN
range,
SN74LV74A
LOAD
CAPACITANCE
PRE or CLR
tpd
free-air
MAX
MIN
MAX
UNIT
MHz
6.9*
12.3*
1*
14.5*
1
14.5
7.9*
11.9*
1*
14*
1
14
9.2
15.8
1
18
1
18
10.2
15.4
1
17.5
1
17.5
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
TA = 25°C
tpd
CLK
PRE or CLR
CLK
temperature
SN54LV74A
MIN
TYP
CL = 15 pF
130*
180*
110*
110
CL = 50 pF
90
140
75
75
Q or Q
CL = 15 pF
Q or Q
CL = 50 pF
MAX
MIN
range,
SN74LV74A
LOAD
CAPACITANCE
PRE or CLR
tpd
free-air
MAX
MIN
MAX
UNIT
MHz
5*
7.7*
1*
9*
1
9
5.6*
7.3*
1*
8.5*
1
8.5
6.6
9.7
1
11
1
11
7.2
9.3
1
10.5
1
10.5
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6)
SN74LV74A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.1
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
0
−0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
3.2
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
V
2.31
V
0.99
V
TYP
UNIT
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 10 MHz
VCC
3.3 V
21
5V
23
pF
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
Test
Point
RL = 1 kΩ
From Output
Under Test
CL
(see Note A)
S1
Open
TEST
GND
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
CL
(see Note A)
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
50% VCC
Input
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
tPHL
50% VCC
tPHL
50% VCC
VOL
tPLZ
≈VCC
50% VCC
tPZH
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
50% VCC
50% VCC
tPZL
VOH
In-Phase
Output
Out-of-Phase
Output
0V
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Device Marking
(4/5)
SN74LV74AD
ACTIVE
SOIC
D
14
SN74LV74ADBLE
OBSOLETE
SSOP
DB
14
TBD
Call TI
Call TI
-40 to 85
SN74LV74ADBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74ADBRE4
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74ADBRG4
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74ADE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74ADG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74ADGVR
ACTIVE
TVSOP
DGV
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74ADGVRE4
ACTIVE
TVSOP
DGV
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74ADGVRG4
ACTIVE
TVSOP
DGV
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74ADR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74ADRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74ADRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74ANSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
74LV74A
SN74LV74ANSRG4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
74LV74A
SN74LV74APW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74APWE4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
Addendum-Page 1
LV74A
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
18-Oct-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Device Marking
(4/5)
SN74LV74APWG4
ACTIVE
TSSOP
PW
14
LV74A
SN74LV74APWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 85
SN74LV74APWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74APWRE4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74APWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74APWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74APWTE4
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74APWTG4
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74ARGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LV74A
SN74LV74ARGYRG4
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LV74A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
18-Oct-2013
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV74A :
• Automotive: SN74LV74A-Q1
• Enhanced Product: SN74LV74A-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LV74ADBR
SSOP
DB
14
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
SN74LV74ADGVR
TVSOP
DGV
14
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74LV74ADR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LV74APWR
TSSOP
PW
14
2000
330.0
12.4
7.0
5.6
1.6
8.0
12.0
Q1
SN74LV74APWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV74APWRG4
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV74APWT
TSSOP
PW
14
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV74ARGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV74ADBR
SSOP
DB
14
2000
367.0
367.0
38.0
SN74LV74ADGVR
TVSOP
DGV
14
2000
367.0
367.0
35.0
SN74LV74ADR
SOIC
D
14
2500
367.0
367.0
38.0
SN74LV74APWR
TSSOP
PW
14
2000
364.0
364.0
27.0
SN74LV74APWR
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74LV74APWRG4
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74LV74APWT
TSSOP
PW
14
250
367.0
367.0
35.0
SN74LV74ARGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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