SN74LV86ATPWREP

      
    SCLS567A − JANUARY 2004 − REVISED MAY 2004 D Controlled Baseline D D D D D D Typical VOLP (Output Ground Bounce) − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 105°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† 2-V to 5.5-V VCC Operation 2.3 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Voltage Operation on All Ports D D PW PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y description/ordering information The SN74LV86A is a quadruple 2-input exclusive-OR gate designed for 2-V to 5.5-V VCC operation. This device contains four independent 2-input exclusive-OR gates. It performs the Boolean function Y = A ę B or Y = AB + AB in positive logic. A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output. ORDERING INFORMATION TA ORDERABLE PART NUMBER PACKAGE‡ TOP-SIDE MARKING −40°C to 105°C TSSOP − PW Tape and reel SN74LV86ATPWREP LV86AEP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y L L L L H H H L H H H L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated     ! "#$ !  %#&'" ($) (#"! "  !%$""! %$ *$ $!  $+! !#$! !(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($ $!.  '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
      
    SCLS567A − JANUARY 2004 − REVISED MAY 2004 logic symbol† 1A 1B 2A 2B 3A 3B 4A 4B 1 =1 2 3 1Y 4 6 5 2Y 9 8 10 3Y 12 11 13 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. exclusive-OR logic An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. Exclusive OR =1 These are five equivalent exclusive-OR symbols valid for an ’LV86A gate in positive logic; negation can be shown at any two ports. Logic-Identity Element Even-Parity Element = 2k The output is active (low) if all inputs stand at the same logic level (i.e., A = B). The output is active (low) if an even number of inputs (i.e., 0 or 2) are active. Odd-Parity Element 2k + 1 The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
      
    SCLS567A − JANUARY 2004 − REVISED MAY 2004 recommended operating conditions (see Note 4) VCC VIH VIL Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V IOH IOL ∆t/∆v MAX 2 5.5 V VCC × 0.7 0.5 VCC × 0.3 VCC × 0.3 Input voltage 0 Output voltage 0 VCC × 0.3 5.5 VCC −50 VCC = 2 V VCC = 2.3 V to 2.7 V µA mA −12 µA 50 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V V V −6 VCC = 2 V VCC = 2.3 V to 2.7 V Input transition rise or fall rate V −2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low-level output current V VCC × 0.7 VCC × 0.7 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V High-level output current UNIT 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V Low-level input voltage VI VO MIN 6 mA 12 0 200 0 100 0 20 ns/V TA Operating free-air temperature −40 105 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VCC IOH = −50 µA IOH = −2 mA 2 V to 5.5 V IOH = −6 mA IOH = −12 mA IOL = 50 µA IOL = 2 mA VI = 5.5 V or GND VI = VCC or GND, Ioff Ci VI or VO = 0 to 5.5 V VI = VCC or GND 2.3 V 3V 2.48 4.5 V 3.8 MAX UNIT V 0.1 2.3 V 0.4 3V 0.44 4.5 V 0.55 V 0 to 5.5 V ±1 µA 5.5 V 20 µA 0 5 µA IO = 0 3.3 V POST OFFICE BOX 655303 TYP 2 V to 5.5 V IOL = 6 mA IOL = 12 mA II ICC MIN VCC−0.1 2 • DALLAS, TEXAS 75265 1.4 pF 3 
      
    SCLS567A − JANUARY 2004 − REVISED MAY 2004 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A or B Y CL = 50 pF MIN tpd FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A or B Y CL = 50 pF PARAMETER tpd TO (OUTPUT) LOAD CAPACITANCE A or B Y CL = 50 pF 14.5 free-air MIN 5.3 MAX UNIT 1 26.5 ns range, MIN MAX UNIT 1 16.5 ns temperature TA = 25°C TYP MAX range, MIN temperature TA = 25°C TYP MAX 7.4 FROM (INPUT) 22.6 free-air MIN switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) temperature TA = 25°C TYP MAX 10.5 switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER free-air MIN MAX 8.8 1 10 MIN range, UNIT ns noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) TYP MAX VOL(P) VOL(V) Quiet output, maximum dynamic VOL PARAMETER 0.2 0.8 V Quiet output, minimum dynamic VOL −0.1 −0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 3.1 High-level dynamic input voltage UNIT V 2.31 V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. 0.99 V VCC 3.3 V TYP UNIT 5V 8.8 operating characteristics, TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz 8.4 pF 
      
    SCLS567A − JANUARY 2004 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output 0V VOH 50% VCC VOL 50% VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPLZ tPZL Output Waveform 1 S1 at VCC (see Note B) tPLH VOH 50% VCC VOL VCC Output Control ≈VCC 50% VCC tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LV86ATPWREP ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LV86AEP V62/04694-01XE ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LV86AEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of