SN74LVC00ADR

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN54LVC00A, SN74LVC00A SCAS279R – JANUARY 1993 – REVISED FEBRUARY 2016 SNx4LVC00A Quadruple 2-Input Positive-NAND Gates 1 Features 2 Applications • • • • • • • • 1 • • • • • • • Operate From 1.65 V to 3.6 V Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C Inputs Accept Voltages to 5.5 V Max tpd of 4.3 ns at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Latch-Up Performance Exceeds 250 mA Per JESD 17 On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters. ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model – 200-V Machine Model – 1000-V Charged-Device Model • • • • • AV Receivers Audio Docks: Portable Blu-ray Players and Home Theater MP3 Players or Recorder s Personal Digital Assistants (PDAs) Power: Telecom/Server AC/DC Supply: Single Controller: Analog and Digital Solid State Drives (SSDs): Client and Enterprise TVs: LCD, Digital, and High-Definition (HDTV) Tablets: Enterprise Video Analytics: Server Wireless Headsets, Keyboards, and Mice 3 Description The SN54LVC00A quadruple 2-input positive-NAND gate is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC00A quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation. The SNx4LVC00A devices perform the Boolean function Y = A × B or Y = A + B in positive logic. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. Device Information(1) PART NUMBER SNx4LVC00A PACKAGE BODY SIZE (NOM) SOIC (14) 8.65 mm × 3.91 mm SSOP (14) 6.20 mm × 5.30 mm SOP (14) 10.30 mm × 5.30 mm TSSOP (14) 5.00 mm × 4.40 mm VQFN (14) 3.50 mm × 3.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic A Y B A Y B A Y B A Y B 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54LVC00A, SN74LVC00A SCAS279R – JANUARY 1993 – REVISED FEBRUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 Absolute Maximum Ratings ..................................... 4 7.2 ESD Ratings ............................................................ 4 7.3 Recommended Operating Conditions, SN54LVC00A ................................................................................... 5 7.4 Recommended Operating Conditions, SN74LVC00A ................................................................................... 5 7.5 Thermal Information .................................................. 6 7.6 Electrical Characteristics, SN54LVC00A .................. 6 7.7 Electrical Characteristics, SN74LVC00A .................. 6 7.8 Switching Characteristics, SN54LVC00A ................. 7 7.9 Switching Characteristics, SN74LVC00A ................. 7 7.10 Operating Characteristics........................................ 7 7.11 Typical Characteristics ............................................ 7 8 9 Parameter Measurement Information .................. 8 Detailed Description .............................................. 9 9.1 9.2 9.3 9.4 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 9 9 9 9 10 Application and Implementation........................ 10 10.1 Application Information.......................................... 10 10.2 Typical Application ............................................... 10 11 Power Supply Recommendations ..................... 11 12 Layout................................................................... 11 12.1 Layout Guidelines ................................................. 11 12.2 Layout Example .................................................... 11 13 Device and Documentation Support ................. 12 13.1 13.2 13.3 13.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 12 12 12 12 14 Mechanical, Packaging, and Orderable Information ........................................................... 12 5 Revision History Changes from Revision Q (December 2014) to Revision R Page • Added Junction temperature row to Absolute Maximum Ratings table.................................................................................. 4 • Changed statement of "open drain: to "maximum sink and source current" statement in Overview of Detailed Description section ................................................................................................................................................................. 9 • Deleted "open drain" from Application Information section .................................................................................................. 10 Changes from Revision P (July 2005) to Revision Q Page • Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 • Deleted Ordering Information table. ....................................................................................................................................... 1 • Added Military Disclaimer to Features.................................................................................................................................... 1 2 Submit Documentation Feedback Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC00A SN74LVC00A SN54LVC00A, SN74LVC00A www.ti.com SCAS279R – JANUARY 1993 – REVISED FEBRUARY 2016 6 Pin Configuration and Functions 3 12 4 11 5 10 6 9 7 8 1Y NC 2A NC 2B 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 1B 1Y 2A 2B 2Y VCC VCC 4B 4A 4Y 3B 3A 3Y 1 14 2 13 4B 3 12 4A 4Y 4 11 5 10 3B 9 3A 6 7 8 3Y 13 1A 14 2 GND 1 SN74LVC00A . . . RGY PACKAGE (TOP VIEW) 2Y GND NC 3Y 3A 1A 1B 1Y 2A 2B 2Y GND SN54LVC00A . . . FK PACKAGE (TOP VIEW) 1B 1A NC VCC 4B SN54LVC00A . . . J OR W PACKAGE SN74LVC00A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW) NC - No internal connection Pin Functions PIN NAME SN74LVC00A SN54LVC00A TYPE DESCRIPTION D, DB, NS, PW RGY J, W FK 1A 1 1 1 2 I Gate 1 input 1B 2 2 2 3 I Gate 1 input 1Y 3 3 3 4 O Gate 1 output 2A 4 4 4 6 I Gate 2 input 2B 5 5 5 8 I Gate 2 input 2Y 6 6 6 9 O Gate 2 output GND 7 7 7 10 — Ground Pin 3Y 8 8 8 12 — Power Pin 3A 9 9 9 13 I Gate 4 input 3B 10 10 10 14 I Gate 4 input 4Y 11 11 11 16 O Gate 4 output 4A 12 12 12 18 I Gate 3 input 4B 13 13 13 19 I Gate 3 input VCC 14 14 14 20 O Gate 3 output — No Connection 1 5 NC — — — 7 11 15 17 Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC00A SN74LVC00A Submit Documentation Feedback 3 SN54LVC00A, SN74LVC00A SCAS279R – JANUARY 1993 – REVISED FEBRUARY 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX Supply voltage range –0.5 6.5 UNIT V (2) –0.5 6.5 V –0.5 VCC + 0.5 VI Input voltage range VO Output voltage range (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA VCC Continuous current through GND ±100 mA 500 mW 150 °C 150 °C (4) (5) Ptot Power dissipation Tstg Storage temperature range Tj Junction Temperature (1) (2) (3) (4) (5) TA = –40°C to 125°C -65 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the Recommended Operating Conditions table. For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K. For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K. 7.2 ESD Ratings VALUE V(ESD) (1) (2) 4 Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC00A SN74LVC00A SN54LVC00A, SN74LVC00A www.ti.com SCAS279R – JANUARY 1993 – REVISED FEBRUARY 2016 7.3 Recommended Operating Conditions, SN54LVC00A over operating free-air temperature range (unless otherwise noted) (1) SN54LVC00A –55°C to 125°C MAX 2 3.6 Operating VCC Supply voltage VIH High-level input voltage VCC = 2.7 V to 3.6 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V VI Input voltage VO Output voltage Data retention only IOH High-level output current IOL Low-level output current (1) MIN UNIT V 1.5 2 V 0.8 V 0 5.5 V 0 VCC V VCC = 2.7 V –12 VCC = 3 V –24 VCC = 2.7 V 12 VCC = 3 V 24 mA mA All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 7.4 Recommended Operating Conditions, SN74LVC00A over operating free-air temperature range (unless otherwise noted) (1) SN74LVC00A TA = 25°C VCC Supply voltage VIH High-level input voltage Operating Data retention only UNIT MAX MIN MAX MIN MAX 1.65 3.6 1.65 3.6 1.65 3.6 1.5 1.5 0.65 × VCC 0.65 × VCC 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 VCC = 2.7 V to 3.6 V 2 2 2 VCC = 1.65 V to 1.95 V VIL –40°C to 125°C MIN 1.5 VCC = 1.65 V to 1.95 V Low-level input voltage –40°C to 85°C V V 0.35 × VCC 0.35 × VCC 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 0.7 0.7 VCC = 2.7 V to 3.6 V 0.8 0.8 0.8 V VI Input voltage 0 5.5 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC 0 VCC V IOH IOL (1) High-level output current Low-level output current VCC = 1.65 V –4 –4 VCC = 2.3 V –8 –8 –4 –8 VCC = 2.7 V –12 –12 –12 VCC = 3 V –24 –24 –24 VCC = 1.65 V 4 4 4 VCC = 2.3 V 8 8 8 VCC = 2.7 V 12 12 12 VCC = 3 V 24 24 24 mA mA All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC00A SN74LVC00A Submit Documentation Feedback 5 SN54LVC00A, SN74LVC00A SCAS279R – JANUARY 1993 – REVISED FEBRUARY 2016 www.ti.com 7.5 Thermal Information SN74LVC00A THERMAL METRIC (1) RθJA (1) D DB NS PW RGY 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 86 96 76 113 47 Junction-to-ambient thermal resistance UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.6 Electrical Characteristics, SN54LVC00A over recommended operating free-air temperature range (unless otherwise noted) SN54LVC00A PARAMETER TEST CONDITIONS VCC –55°C to 125°C MIN IOH = –100 µA VOH VOL 2.7 V to 3.6 V VCC – 0.2 2.7 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 2.7 V to 3.6 V IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3V 0.55 IOH = –12 mA II VI = 5.5 V or GND ICC VI = VCC or GND, IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND ΔICC UNIT MAX V 0.2 3.6 V V ±5 µA 3.6 V 10 µA 2.7 V to 3.6 V 500 µA 7.7 Electrical Characteristics, SN74LVC00A over recommended operating free-air temperature range (unless otherwise noted) SN74LVC00A PARAMETER TEST CONDITIONS VCC TA = 25°C MIN IOH = –100 µA VOH MIN MAX –40°C to 125°C MIN VCC – 0.2 VCC – 0.2 VCC – 0.3 1.65 V 1.29 1.2 1.05 IOH = –8 mA 2.3 V 1.9 1.7 1.55 2.7 V 2.2 2.2 2.05 2.25 UNIT MAX V 3V 2.4 2.4 IOH = –24 mA 3V 2.3 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.1 0.2 IOL = 4 mA 1.65 V 0.24 0.45 0.6 IOL = 8 mA 2.3 V 0.3 0.7 0.85 IOL = 12 mA 2.7 V 0.4 0.4 0.6 3V IOL = 24 mA 2 0.3 V 0.55 0.55 0.8 II VI = 5.5 V or GND 3.6 V ±1 ±5 ±20 µA ICC VI = VCC or GND, IO = 0 3.6 V 1 10 40 µA 500 500 5000 µA ΔICC Ci 6 –40°C to 85°C MAX IOH = –4 mA IOH = –12 mA VOL 1.65 V to 3.6 V TYP One input at VCC – 0.6 V, Other inputs at VCC or GND VI = VCC or GND Submit Documentation Feedback 2.7 V to 3.6 V 3.3 V 5 pF Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC00A SN74LVC00A SN54LVC00A, SN74LVC00A www.ti.com SCAS279R – JANUARY 1993 – REVISED FEBRUARY 2016 7.8 Switching Characteristics, SN54LVC00A over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN54LVC00A FROM (INPUT) PARAMETER TO (OUTPUT) VCC –55°C to 125°C MIN tpd A or B 2.7 V Y UNIT MAX 5.1 3.3 V ± 0.3 V 1 4.3 ns 7.9 Switching Characteristics, SN74LVC00A over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN74LVC00A PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN tpd A or B Y tsk(o) –40°C to 85°C TYP MAX –40°C to 125°C MIN MAX MIN MAX 1.8 V ± 0.15 V 1 6 12 1 12.5 1 14 2.5 V ± 0.2 V 1 4.6 5.9 1 6.4 1 7.9 2.7 V 1 4.3 4.9 1 5.1 1 6.5 3.3 V ± 0.3 V 1 3.5 4.1 1 4.3 1 5.5 3.3 V ± 0.3 V 1 1.5 UNIT ns ns 7.10 Operating Characteristics TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate f = 10 MHz VCC TYP 1.8 V 18 2.5 V 18 3.3 V 19 UNIT pF 7.11 Typical Characteristics 8 7 TPD (ns) 6 5 4 3 2 1 TPD 0 1.5 2.0 2.5 3.0 3.5 VCC Input (V) 4.0 C001 Figure 1. TPD vs VCC (TA = 25°C) Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC00A SN74LVC00A Submit Documentation Feedback 7 SN54LVC00A, SN74LVC00A SCAS279R – JANUARY 1993 – REVISED FEBRUARY 2016 www.ti.com 8 Parameter Measurement Information VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL VΔ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V VOH VM Output VM VOL VM tPLZ VLOAD/2 VM tPZH VOH Output VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VΔ VOL tPHZ VM VOH – VΔ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. t PLZ and t PHZ are the same as t dis. F. t PZL and tPZH are the same as t en . G. t PLH and t PHL are the same as tpd . H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC00A SN74LVC00A SN54LVC00A, SN74LVC00A www.ti.com SCAS279R – JANUARY 1993 – REVISED FEBRUARY 2016 9 Detailed Description 9.1 Overview The maximum sink and source current is 24mA. Inputs can be driven from 1.8-V, 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of this device as translators in a mixed-system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 9.2 Functional Block Diagram Logic Diagram, Each Gate (Positive Logic) A Y B 9.3 Feature Description • • • Wide operating voltage range – Operates from 1.65 V to 3.6 V Allows up or down voltage translation – Inputs and outputs accept voltages to 5.5 V Ioff feature – Allows voltages on the inputs and outputs when VCC is 0 V 9.4 Device Functional Modes Table 1. Function Table (Each Gate) INPUTS OUTPUT Y A B H H L L X H X L H Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC00A SN74LVC00A Submit Documentation Feedback 9 SN54LVC00A, SN74LVC00A SCAS279R – JANUARY 1993 – REVISED FEBRUARY 2016 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information SN74LVC00A is a high-drive CMOS device that can be used for a multitude of buffer-type functions. It can produce 24 mA of drive current at 3.3 V. Therefore, this device is ideal for driving multiple inputs and for highspeed applications up to 100 MHz. The inputs and outputs are 5.5-V tolerant allowing the device to translate up to 5.5 V or down to VCC. 10.2 Typical Application 1.65-V to 3.6-V VCC 1A 1B 4A 4B 1Y 4Y Figure 3. Typical NAND Gate Application and Supply Voltage 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads; therefore, routing and load conditions should be considered to prevent ringing. 10.2.2 Detailed Design Procedure 1. Recommended Input Conditions – Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions, SN74LVC00A table. – Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions, SN74LVC00A table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC. 2. Recommend Output Conditions – Load currents should not exceed 25 mA per output and 50 mA total for the part. – Outputs should not be pulled above 5.5 V. 10 Submit Documentation Feedback Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC00A SN74LVC00A SN54LVC00A, SN74LVC00A www.ti.com SCAS279R – JANUARY 1993 – REVISED FEBRUARY 2016 Typical Application (continued) 10.2.3 Application Curves Figure 4. ICC vs Frequency 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions, SN74LVC00A table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices inputs should never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Layout Example specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver. 12.2 Layout Example Vcc Input Unused Input Output Unused Input Output Input Figure 5. Layout Diagram Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC00A SN74LVC00A Submit Documentation Feedback 11 SN54LVC00A, SN74LVC00A SCAS279R – JANUARY 1993 – REVISED FEBRUARY 2016 www.ti.com 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN54LVC00A Click here Click here Click here Click here Click here SN74LVC00A Click here Click here Click here Click here Click here 13.2 Trademarks All trademarks are the property of their respective owners. 13.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Documentation Feedback Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC00A SN74LVC00A PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9753301Q2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629753301Q2A SNJ54LVC 00AFK 5962-9753301QCA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9753301QC A SNJ54LVC00AJ 5962-9753301QDA ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9753301QD A SNJ54LVC00AW 5962-9753301VDA ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9753301VD A SNV54LVC00AW SN74LVC00AD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples SN74LVC00ADBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples SN74LVC00ADBRG4 ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples SN74LVC00ADE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples SN74LVC00ADR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples SN74LVC00ADRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples SN74LVC00ADT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples SN74LVC00ANSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples SN74LVC00ANSRG4 ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples SN74LVC00APW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples SN74LVC00APWE4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples SN74LVC00APWG4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples SN74LVC00APWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LC00A Samples Addendum-Page 1 Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Jun-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LVC00APWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples SN74LVC00APWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples SN74LVC00APWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples SN74LVC00ARGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC00A Samples SNJ54LVC00AFK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629753301Q2A SNJ54LVC 00AFK SNJ54LVC00AJ ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9753301QC A SNJ54LVC00AJ SNJ54LVC00AW ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9753301QD A SNJ54LVC00AW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of