SN74LVC07AQPWRQ1

SN74LVC07A-Q1 www.ti.com SCAS783D – OCTOBER 2004 – REVISED JULY 2012 HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS Check for Samples: SN74LVC07A-Q1 FEATURES 1 • • • • D OR PW PACKAGE (TOP VIEW) Qualified for Automotive Applications Operates From 1.65 V to 5 V Inputs and Open-Drain Outputs Accept Voltages up to 5.5 V Latch-Up Performance Exceeds 250 mA Per JESD 17 DESCRIPTION/ORDERING INFORMATION This hex buffer/driver is designed for 1.65-V to 5.5-V VCC operation. The outputs of the SN74LVC07A device are open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA. Inputs can be driven from 1.8-V, 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of this device as a translator in a mixed-system environment. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 125°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC – D Reel of 2500 SN74LVC07AQDRQ1 LVC07AQ TSSOP – PW Reel of 2000 SN74LVC07AQPWRQ1 LVC07AQ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Table 1. FUNCTION TABLE (EACH BUFFER/DRIVER) INPUT A OUTPUT Y H H L L LOGIC DIAGRAM, EACH BUFFER/DRIVER (POSITIVE LOGIC) A Y 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2012, Texas Instruments Incorporated SN74LVC07A-Q1 SCAS783D – OCTOBER 2004 – REVISED JULY 2012 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Output voltage range –0.5 6.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (3) Tstg Storage temperature range (1) (2) (3) D package 86 PW package 113 –65 150 °C/W °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 5.5 UNIT V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V V 0.35 × VCC VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 VI Input voltage 0 5.5 V VO Output voltage 0 5.5 V VCC = 2.7 V to 3.6 V IOL TA (1) 2 Low-level output current Operating free-air temperature V 0.8 VCC = 1.65 V 4 VCC = 2.3 V 12 VCC = 2.7 V 12 VCC = 3 V 24 –40 125 mA °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Copyright © 2004–2012, Texas Instruments Incorporated SN74LVC07A-Q1 www.ti.com SCAS783D – OCTOBER 2004 – REVISED JULY 2012 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOL = 100 μA 0.2 1.65 V 0.45 2.3 V 0.7 2.7 V 0.4 3V 0.65 IOL = 12 mA IOL = 24 mA II ICC ΔICC Ci (1) MAX 1.65 V to 3.6 V IOL = 4 mA VOL MIN TYP (1) VCC UNIT V VI = 5.5 V or GND 3.6 V ±5 μA VI = VCC or GND, IO = 0 3.6 V 10 μA 500 μA One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V VI = VCC or GND 3.3 V 5 pF All typical values are at VCC = 3.3 V, TA = 25°C. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX MIN MAX 1 3.5 1 2.8 VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX MIN MAX 3 1 2.9 UNIT ns Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance per buffer/driver Copyright © 2004–2012, Texas Instruments Incorporated TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP f = 10 MHz 1.8 2 2.5 UNIT pF 3 SN74LVC07A-Q1 SCAS783D – OCTOBER 2004 – REVISED JULY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open TEST S1 tPZL (see Note F) 2 × VCC tPLZ (see Note G) 2 × VCC tPHZ/tPZH 2 × VCC GND CL = 30 pF (see Note A) 1 kΩ LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 Output Waveform 2 S1 at 2 × VCC (see Note B) VOL + 0.15 V VOL tPHZ tPZH VCC VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VCC VCC − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VCC/2. G. tPLZ is measured at VOL + 0.15 V. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 Copyright © 2004–2012, Texas Instruments Incorporated SN74LVC07A-Q1 www.ti.com SCAS783D – OCTOBER 2004 – REVISED JULY 2012 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open TEST S1 tPZL (see Note F) 2 × VCC tPLZ (see Note G) 2 × VCC tPHZ/tPZH 2 × VCC GND CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 Output Waveform 2 S1 at 2 × VCC (see Note B) VOL + 0.15 V VOL tPHZ tPZH VCC VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VCC VCC − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VCC/2. G. tPLZ is measured at VOL + 0.15 V. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Copyright © 2004–2012, Texas Instruments Incorporated 5 SN74LVC07A-Q1 SCAS783D – OCTOBER 2004 – REVISED JULY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION VCC = 2.7 and 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPZL (see Note F) 6V tPLZ (see Note G) 6V tPHZ/tPZH 6V LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 0V 0V 2.7 V 1.5 V 1.5 V 0V 1.5 V 1.5 V 0V tPLH VOL 1.5 V 0V tPLZ 3V 1.5 V Output Waveform 2 S1 at 6 V (see Note B) VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 2.7 V 1.5 V Output Waveform 1 S1 at 6 V (see Note B) tPHL 3V 1.5 V Output Control (low-level enabling) tPZL 2.7 V Output VOLTAGE WAVEFORMS PULSE DURATION th VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 1.5 V tsu Data Input 1.5 V Input 3V 1.5 V 2.7 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at 1.5 V. G. tPLZ is measured at VOL + 0.3 V. H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms 6 Copyright © 2004–2012, Texas Instruments Incorporated SN74LVC07A-Q1 www.ti.com SCAS783D – OCTOBER 2004 – REVISED JULY 2012 PARAMETER MEASUREMENT INFORMATION VCC = 5 V ± 0.5 V S1 500 Ω From Output Under Test 2 × VCC Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPZL (see Note F) tPLZ (see Note G) 2 × VCC 2 × VCC tPHZ/tPZH 7V LOAD CIRCUIT tw 3V 3V Timing Input 1.5 V 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH 1.5 V VOL VCC/2 0V tPLZ VCC VCC/2 tPZH 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC VCC/2 Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL 3.5 V Output Output Control (low-level enabling) tPZL 3V Input VOLTAGE WAVEFORMS PULSE DURATION th 1.5 V 1.5 V 0V 0V tsu Data Input 1.5 V Input Output Waveform 2 S1 at 7 V (see Note B) VOL + 0.3 V VOL tPHZ 3.5 V 1.5 V 3.2 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. t PZL is measured at VCC/2. G. tPLZ is measured at VOL + 0.3 V. H. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms Copyright © 2004–2012, Texas Instruments Incorporated 7 SN74LVC07A-Q1 SCAS783D – OCTOBER 2004 – REVISED JULY 2012 www.ti.com REVISION HISTORY Changes from Revision C (December, 2007) to Revision D Page • Changed from "Operates From 1.65 V to 3.6 V" to "Operates From 1.65 V to 5 V" ............................................................ 1 • Changed from "This hex buffer/driver is designed for 1.65-V to 3.6-V VCC operation" to "This hex buffer/driver is designed for 1.65-V to 5.5-V VCC operation" ........................................................................................................................ 1 • Changed supply voltage max value from 3.6 to 5.5 ............................................................................................................. 2 • Added 4th PMI image ........................................................................................................................................................... 7 8 Copyright © 2004–2012, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LVC07AQPWRG4Q1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC07AQ SN74LVC07AQPWRQ1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC07AQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of