SN74LVC08A-Q1
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES480C − AUGUST 2003 − REVISED JANUARY 2008
D Qualified for Automotive Applications
D ESD Protection Exceeds 2000 V Per
D
D
D
D
D
D OR PW PACKAGE
(TOP VIEW)
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.1 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
2 V at VCC = 3.3 V, TA = 25°C
1A
1B
1Y
2A
2B
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
description/ordering information
The SN74LVC08A-Q1 quadruple 2-input positive-AND gate is designed for 2.7-V to 3.6-V VCC operation.
The device performs the Boolean function Y + A • B or Y + A ) B in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator
in a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION†
40°C to 125°C
−40°C
ORDERABLE
PART NUMBER
PACKAGE‡
TA
TOP-SIDE
MARKING
SOIC − D
Reel of 2500
SN74LVC08AQDRQ1
LVC08AQ
TSSOP − PW
Reel of 2000
SN74LVC08AQPWRQ1
LVC08AQ
†
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
logic diagram, each gate (positive logic)
A
Y
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74LVC08A-Q1
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES480C − AUGUST 2003 − REVISED JANUARY 2008
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
Operating
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
VI
Input voltage
VO
Output voltage
IOH
High level output current
High-level
IOL
Low level output current
Low-level
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
Data retention only
MIN
MAX
2
3.6
V
1.5
2
V
0.8
V
0
5.5
V
0
VCC
V
VCC = 2.7 V
−12
VCC = 3 V
−24
VCC = 2.7 V
12
VCC = 3 V
24
Q suffix
UNIT
0
8
−40
125
mA
mA
ns/V
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303
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SN74LVC08A-Q1
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES480C − AUGUST 2003 − REVISED JANUARY 2008
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −100 μA
VOH
2.7 V to 3.6 V
VCC−0.2
2.7 V
2.2
3V
2.4
3V
2.2
IOH = −12
12 mA
IOH = −24 mA
VOL
†
MIN
VCC
TYP†
MAX
UNIT
V
IOL = 100 μA
2.7 V to 3.6 V
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3V
0.55
3.6 V
±5
μA
3.6 V
10
μA
2.7 V to 3.6 V
500
μA
II
VI = 5.5 V or GND
ICC
VI = VCC or GND,
ΔICC
One input at VCC − 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
IO = 0
0.2
3.3 V
5
V
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
MIN
MAX
4.8
1
4.1
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
POST OFFICE BOX 655303
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
9.8
10
UNIT
pF
3
SN74LVC08A-Q1
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES480C − AUGUST 2003 − REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION
VLOAD
RL
From Output
Under Test
CL
(see Note A)
S1
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
2.7 V
2.7 V
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
VΔ
1.5 V
1.5 V
6V
6V
50 pF
50 pF
500 Ω
500 Ω
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VΔ
VOL
tPHZ
VM
VOH − VΔ
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVC08AQPWRG4Q1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC08AQ
SN74LVC08AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC08AQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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