SN74LVC138ADBRE4

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN54LVC138A, SN74LVC138A SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 SN74LVC138A 3-Line to 8-Line Decoders Demultiplexers 1 Features 3 Description • • • • The SN74LVC138A devices are designed for highperformance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. 1 • • Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 5.8 ns at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Latch-Up Performance Exceeds 250 mA Per JESD 17 Device Information(1) 2 Applications • • • • • • PART NUMBER LED Displays Servers White Goods Power Infrastructure Building Automation Factory Automation SNx4LVC138A PACKAGE BODY SIZE (NOM) LCCC (20) 8.89 mm × 8.89 mm CDIP (16) 19.56 mm × 6.92 mm CFP (16) 10.30 mm × 6.73 mm SOIC (16) 9.90 mm × 3.91 mm SSOP (16) 6.20 mm × 5.30 mm TVSOP (16) 3.60 mm × 4.40 mm BGA MICROSTAR JUNIOR (20) 4.00 mm × 3.00 mm TSSOP (16) 5.00 mm × 4.40 mm UQFN (16) 2.60 mm × 1.80 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) 15 A 14 Select Inputs B C 13 3 12 10 Enable Inputs 6 4 G2A G2B Y1 2 11 G1 Y0 1 9 7 Y2 Y3 Data Outputs Y4 Y5 Y6 Y7 5 Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages. Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54LVC138A, SN74LVC138A SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 5 5 6 6 7 7 7 8 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics—SN54LVC138A .............. Switching Characteristics—SN74LVC138A .............. Operating Characteristics.......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 9 Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagram ....................................... 10 8.3 Feature Description................................................. 10 8.4 Device Functional Modes........................................ 11 9 Application and Implementation ........................ 12 9.1 Application Information............................................ 12 9.2 Typical Application .................................................. 12 10 Power Supply Recommendations ..................... 13 11 Layout................................................................... 13 11.1 Layout Guidelines ................................................. 13 11.2 Layout Example .................................................... 13 12 Device and Documentation Support ................. 14 12.1 12.2 12.3 12.4 12.5 12.6 Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 14 14 14 14 14 14 13 Mechanical, Packaging, and Orderable Information ........................................................... 14 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision V (November 2013) to Revision W Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Deleted Ordering Information table; see Packaging Ordering Addendum at the end of the data sheet................................ 1 • Changed RθJA values from: 73 to 86.8 (D), 82 to 100.1 (DB), 120 to 122.1 (DGV), 78 to 84 (ZQN), 108 to 108.9 (PW) ....................................................................................................................................................................................... 6 • Deleted RθJA values for NS and RGY packages ..................................................................................................................... 6 Changes from Revision U (OCTOBER 2012) to Revision V Page • Updated document to new TI data sheet format - no specification changes. ........................................................................ 1 • Removed Ordering Information table ..................................................................................................................................... 1 • Added ESD warning ............................................................................................................................................................... 1 2 Submit Documentation Feedback Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC138A SN74LVC138A SN54LVC138A, SN74LVC138A www.ti.com SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 5 Pin Configuration and Functions SN54LVC138A . . . J OR W PACKAGE SN74LVC138A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 4 13 5 12 6 11 7 10 8 9 A VCC 1 16 15 3 14 4 13 5 12 6 11 7 10 B A NC VCC Y0 Y0 Y1 Y2 Y3 Y4 Y5 17 6 16 7 15 8 14 9 10 11 12 13 Y1 Y2 NC Y3 Y4 12 11 10 9 Y2 13 8 GND Y1 14 7 Y7 Y0 15 VCC 16 6 G1 5 G2B 1 2 3 4 A B C 9 Y6 GND 5 SN54LVC138A...RSV PACKAGE (TOP VIEW) 2 8 2 1 20 19 18 NC - No internal connection SN74LVC138A . . . RGY PACKAGE (TOP VIEW) B C G2A G2B G1 Y7 4 Y6 14 3 C G2A NC G2B G1 G2A 3 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y5 15 Y4 16 2 Y7 GND NC Y6 Y5 1 Y3 A B C G2A G2B G1 Y7 GND SN54LVC138A . . . FK PACKAGE (TOP VIEW) GQN OR ZQN PACKAGE (TOP VIEW) 1 2 3 4 A B C D E Table 1. Pin Assignments for ZQN (BGA) 1 (1) 2 3 4 A B A VCC Y0 B C NC (1) NC (1) Y1 C G2B G2A Y3 Y2 D G1 E GND NC (1) Y7 NC (1) Y6 Y4 Y5 NC - No internal connection Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC138A SN74LVC138A Submit Documentation Feedback 3 SN54LVC138A, SN74LVC138A SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 www.ti.com Pin Functions PIN SOIC, SSOP, TVSOP, SO, TSSOP, VQFN, UQFN LCCC BGA MICROSTAR JUNIOR I/O A 1 2 A2 I Select input A (least significant bit) B 2 3 A1 I Select input B C 3 4 B1 I Select input C (most significant bit) G2A 4 5 C2 I Active low enable A G2B 5 7 C1 I Active low enable B G1 6 8 D1 I Active high enable GND 8 10 E1 — Ground NC — 1, 11, 16 B2, B3, D2, D3 — No internal connection VCC 16 20 A3 — Supply voltage Y0 15 19 A4 O Output 0 (least significant bit) Y1 14 18 B4 O Output 1 Y2 13 17 C4 O Output 2 Y3 12 15 C3 O Output 3 Y4 11 14 D4 O Output 4 Y5 10 13 E4 O Output 5 Y6 9 12 E3 O Output 6 Y7 7 9 E2 O Output 7 (most significant bit) NAME 4 Submit Documentation Feedback DESCRIPTION Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC138A SN74LVC138A SN54LVC138A, SN74LVC138A www.ti.com SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX UNIT Supply voltage –0.5 6.5 V (2) –0.5 6.5 V –0.5 VCC + 0.5 V VI Input voltage VO Output voltage (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCC or GND ±100 mA 150 °C 150 °C Tstg Storage temperature TJ Junction temperature (1) (2) (3) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 1000 Machine model (MM) 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC138A SN74LVC138A Submit Documentation Feedback 5 SN54LVC138A, SN74LVC138A SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 www.ti.com 6.3 Recommended Operating Conditions VCC Operating Supply voltage MIN MAX SN54LVC138A (1) 2 3.6 SN74LVC138A (1) 1.65 3.6 Data retention only VIH High-level input voltage UNIT V 1.5 VCC = 1.65 V to 1.95 V SN74LVC138A (1) 0.65 × VCC VCC = 2.3 V to 2.7 V SN74LVC138A (1) 1.7 VCC = 2.7 V to 3.6 V V 2 VCC = 1.65 V to 1.95 V SN74LVC138A (1) 0.35 × VCC VCC = 2.3 V to 2.7 V SN74LVC138A (1) 0.7 VIL Low-level input voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 2.7 V to 3.6 V IOH High-level output current 0.8 (1) VCC = 1.65 V SN74LVC138A VCC = 2.3 V SN74LVC138A (1) –4 –8 VCC = 2.7 V –12 VCC = 3 V IOL Low-level output current Δt/Δv Input transition rise or fall rate Operating free-air temperature TA (1) V mA –24 VCC = 1.65 V SN74LVC138A (1) VCC = 2.3 V SN74LVC138A (1) 4 8 VCC = 2.7 V 12 VCC = 3 V 24 10 SN54LVC138A (1) –55 125 SN74LVC138A (1) –40 85 mA ns/V °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs. 6.4 Thermal Information SNx4LVC138A THERMAL METRIC (1) FK (LCCC) J (CDIP) W (CFP) D (SOIC) DB (SSOP) DGV (TVSOP) ZQN (BGA MICROSTAR JUNIOR) PW (TSSOP) RSV (UQFN) 20 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 20 PINS 16 PINS 16 PINS UNIT RθJA Junction-to-ambient thermal resistance 79.2 85.8 138.0 86.8 100.1 122.1 84 108.9 168.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 56.5 49.3 74.6 47.9 50.6 47.4 56.9 42.5 78.2 °C/W RθJB Junction-to-board thermal resistance 55.2 64.9 127.7 43.8 50.7 53.8 46.1 54.5 96.4 °C/W ψJT Junction-to-top characterization parameter 49.8 37.4 50 15.7 14.3 4.6 3 4.4 4.2 °C/W ψJB Junction-to-board characterization parameter 55.0 69.5 115.7 43.5 50.1 53.2 48.9 53.8 96.5 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC138A SN74LVC138A SN54LVC138A, SN74LVC138A www.ti.com SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH High-level output voltage VCC SN74LVC138A 1.65 V to 3.6 V VCC – 0.2 VCC – 0.2 SN54LVC138A 2.7 V to 3.6 V IOH = –4 mA SN74LVC138A 1.65 V 1.2 IOH = –8 mA SN74LVC138A 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2.2 IOH = –12 mA IOH = –24 mA Low-level output voltage TYP (1) MAX UNIT V SN74LVC138A 1.65 V to 3.6 V SN54LVC138A 2.7 V to 3.6 V 0.2 IOL = 4 mA SN74LVC138A 1.65 V 0.45 IOL = 8 mA SN74LVC138A 2.3 V 0.7 IOL = 100 µA VOL MIN 0.2 IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3V 0.55 V II Input current VI = 5.5 V or GND 3.6 V ±5 µA ICC Supply current VI = VCC or GND, IO = 0 3.6 V 10 µA ΔICC Change in supply current One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 µA Ci Input capacitance VI = VCC or GND (1) 3.3 V 5 pF All typical values are at VCC = 3.3 V, TA = 25°C. 6.6 Switching Characteristics—SN54LVC138A over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) FROM (INPUT) PARAMETER TO (OUTPUT) Propagation (delay) time MIN MAX VCC = 2.7 V A or B or C tpd TEST CONDITIONS 7.9 VCC = 3.3 V ± 0.3 V G2A or G2B Y 1 6.7 VCC = 2.7 V 7.4 VCC = 3.3 V ± 0.3 V 1 6.5 VCC = 2.7 V G1 UNIT ns 6.4 VCC = 3.3 V ± 0.3 V 1 5.8 6.7 Switching Characteristics—SN74LVC138A over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) FROM (INPUT) PARAMETER TO (OUTPUT) A or B or C tpd Propagation (delay) time G2A or G2B Y G1 tsk(o) Skew (time), output — — TEST CONDITIONS MIN MAX VCC = 1.8 V ± 0.15 V 1 22 VCC = 2.5 V ± 0.2 V 1 9.9 VCC = 2.7 V 1 7.9 VCC = 3.3 V ± 0.3 V 1 6.7 VCC = 1.8 V ± 0.15 V 1 21 VCC = 2.5 V ± 0.2 V 1 9.4 VCC = 2.7 V 1 7.4 VCC = 3.3 V ± 0.3 V 1 6.5 VCC = 1.8 V ± 0.15 V 1 20.3 VCC = 2.5 V ± 0.2 V 1 8.4 VCC = 2.7 V 1 6.4 VCC = 3.3 V ± 0.3 V 1 5.8 VCC = 3.3 V ± 0.3 V Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC138A SN74LVC138A 1 Submit Documentation Feedback UNIT ns ns 7 SN54LVC138A, SN74LVC138A SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 www.ti.com 6.8 Operating Characteristics TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance f = 10 MHz TYP VCC = 1.8 V 25 VCC = 2.5 V 26 VCC = 3.3 V 27 UNIT pF Maximum Propagation Delay - A to Y (ns) 6.9 Typical Characteristics 24 22 20 18 16 14 12 10 8 6 4 1.8 2 2.2 2.4 2.6 2.8 Supply Voltage VCC (V) 3 3.2 3.4 D002 Figure 1. Maximum Propagation Delay vs Supply Voltage 8 Submit Documentation Feedback Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC138A SN74LVC138A SN54LVC138A, SN74LVC138A www.ti.com SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 7 Parameter Measurement Information VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V VOH VM Output VM VOL VM 0V VLOAD/2 VM tPZH VOH Output VM tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + VD VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH − VD VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC138A SN74LVC138A Submit Documentation Feedback 9 SN54LVC138A, SN74LVC138A SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 www.ti.com 8 Detailed Description 8.1 Overview The SNx4LVC138A devices are 3-to-8 decoders and demultiplexers. The three input pins, A, B, and C, select which output is active. The selected output is pulled LOW, while the remaining outputs are all HIGH. The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the requirement for external gates or inverters when expanding. A 24line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. 8.2 Functional Block Diagram 15 A 1 14 Select Inputs B C 13 3 12 10 Enable Inputs 6 9 4 7 G2A G2B Y1 2 11 G1 Y0 Y2 Y3 Data Outputs Y4 Y5 Y6 Y7 5 Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages. Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 3-Line to 8-Line Decoder This device features three binary inputs to select a single active-low output. Three enable pins are also available to enable or disable the outputs. One active high enable and two active low enable pins are available, and any enable pin can be deactivated to force all outputs high. All three enable pins must be active for the output to be enabled. 10 Submit Documentation Feedback Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC138A SN74LVC138A SN54LVC138A, SN74LVC138A www.ti.com SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 Feature Description (continued) 8.3.2 1.65-V to 3.6-V Operation With Inputs up to 5.5 V The SN54LVC138A 3-line to 8-line decoder demultiplexer is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC138A 3-line to 8-line decoder demultiplexer is designed for 1.65-V to 3.6-V VCC operation. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V and 5-V system environment. 8.4 Device Functional Modes Table 2 lists the outputs of the SNx4LVC138A devices based on the possible input configurations. Table 2. Function Table ENABLE INPUTS G1 G2A X X SELECT INPUTS OUTPUTS G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H X X X X H H H H H H H H X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC138A SN74LVC138A Submit Documentation Feedback 11 SN54LVC138A, SN74LVC138A SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN74LVC138A is useful as a scanning column selector for an LED Matrix display as it can be used for the low-side drive of the LED string. The decoder functionality ensures that no more than one output is pulled to a low-level logic voltage so that only a single column is enabled at any point in time. 9.2 Typical Application SER GPIO Inputs SRCLK QA 0V RCLK SN74HC595B QH 3.3V 3.3V HIGH GPIO Inputs A Y0 0V Y7 HIGH B SN74LVC138A HIGH C Copyright © 2016, Texas Instruments Incorporated Figure 3. LED Matrix Driver Application 9.2.1 Design Requirements These devices use CMOS technology and have balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so routing and load conditions must be considered to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions – For switch time specifications, see propagation delay times in Switching Characteristics—SN74LVC138A. – For input voltage level specifications for control inputs, see VIH and VIL in Recommended Operating Conditions. 2. Recommended Output Conditions – Outputs must not be pulled above VCC or below GND. 12 Submit Documentation Feedback Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC138A SN74LVC138A SN54LVC138A, SN74LVC138A www.ti.com SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 Typical Application (continued) 9.2.3 Application Curve 2.4 2.2 VIH MIN VIL MAX Logic Level (V) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 Supply Voltage VCC (V) 3.2 3.4 3.6 D001 Figure 4. Input High and Input Low Thresholds vs Supply Voltage 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal must have a good bypass capacitor to prevent power disturbance. A 0.1-µF bypass capacitor is recommended to be placed close to the VCC terminal. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise; 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power terminal as possible for best results. 11 Layout 11.1 Layout Guidelines Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the trace (resulting in the reflection). It is a given that not all PCB traces can be straight, and so they have to turn corners. Figure 5 shows progressively better techniques of rounding corners. Only the last example maintains constant trace width and minimizes reflections. 11.2 Layout Example BETTER BEST 2W WORST 1W min. W Figure 5. Trace Example Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC138A SN74LVC138A Submit Documentation Feedback 13 SN54LVC138A, SN74LVC138A SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 www.ti.com 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 3. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN54LVC138A Click here Click here Click here Click here Click here SN74LVC138A Click here Click here Click here Click here Click here 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Documentation Feedback Copyright © 1993–2016, Texas Instruments Incorporated Product Folder Links: SN54LVC138A SN74LVC138A PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9752601Q2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629752601Q2A SNJ54LVC 138AFK 5962-9752601QEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9752601QE A SNJ54LVC138AJ 5962-9752601QFA ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9752601QF A SNJ54LVC138AW 5962-9752601VFA ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9752601VF A SNV54LVC138AW SN74LVC138AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A Samples SN74LVC138ADBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A Samples SN74LVC138ADE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A Samples SN74LVC138ADGVR ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A Samples SN74LVC138ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A Samples SN74LVC138ADRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A Samples SN74LVC138ADRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A Samples SN74LVC138ADT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A Samples SN74LVC138ANSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A Samples SN74LVC138ANSRG4 ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A Samples SN74LVC138APW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A Samples SN74LVC138APWG4 ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A Samples SN74LVC138APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 LC138A Samples Addendum-Page 1 Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LVC138APWRE4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A Samples SN74LVC138APWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A Samples SN74LVC138APWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A Samples SN74LVC138ARGYR ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LC138A Samples SN74LVC138ARGYRG4 ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LC138A Samples SN74LVC138ARSVR ACTIVE UQFN RSV 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ZTP Samples SNJ54LVC138AFK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629752601Q2A SNJ54LVC 138AFK SNJ54LVC138AJ ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9752601QE A SNJ54LVC138AJ SNJ54LVC138AW ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9752601QF A SNJ54LVC138AW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of