SN54LVC14A, SN74LVC14A
SCAS285AC – MARCH 1993 – REVISED APRIL 2022
SNx4LVC14A Hex Schmitt-Trigger Inverters
1 Features
3 Description
•
The SN54LVC14A hex Schmitt-trigger inverter is
designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVC14A hex Schmitt-trigger inverter is designed
for 1.65-V to 3.6-V VCC operation.
•
•
•
•
•
•
•
•
Latch-up performance exceeds 100 mA
per JESD 78, Class II
ESD protection exceeds JESD 22
– 2000-V human-body model (A114-A)
– 200-V machine model (A115-A)
– 1000-V charged-device model (C101)
Operate from 1.65 V to 3.6 V VCC
Specified from –40°C to +85°C,
–40°C to 125°C, and –55°C to 125°C
Inputs accept voltages to 5.5 V
Max tpd of 6.4 ns at 3.3 V
Typical VOLP (output ground bounce)
2 V at VCC = 3.3 V, TA = 25°C
On products compliant to MIL-PRF-38535,
all parameters are tested unless otherwise noted.
On all other products, production processing does
not necessarily include testing of all parameters.
The devices contain six independent inverters and
perform the Boolean function Y = A.
Inputs can be driven from either 3.3-V or 5-V
devices. This feature allows the use of these devices
as translators in a mixed 3.3-V or 5-V system
environment.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN54LVC14AFK
LCCC (20)
8.90 mm × 8.90 mm
SN54LVC14AJ
CDIP (14)
20.00 mm × 7.00 mm
SN54LVC14AW
CFP (14)
9.21 mm × 6.30 mm
SN74LVC14ANS
SO (14)
10.20 mm × 5.30 mm
SN74LVC14AD
SOIC (14)
8.65 mm × 6.00 mm
2 Applications
SN74LVC14ADB
SSOP (14)
6.20 mm × 5.30 mm
•
•
•
•
•
•
•
•
•
•
•
•
•
SN74LVC14APW
TSSOP (14)
5.00 mm × 4.40 mm
SN74LVC14ADGV
TVSOP (14)
4.40 mm × 3.60 mm
SN74LVC14ARGY
VQFN (14)
3.50 mm × 3.50 mm
Barcode scanner
Cable solutions
E-books
Embedded PCs
Field transmitter: temperature or pressure sensors
Fingerprint biometrics
HVAC: heating, ventilating, and air conditioning
Network attached storage (NAS)
Server motherboard and PSU
Software defined radio (SDR)
TV: High-definition (HDTV), LCD, and digital
Video communications systems
Wireless data access cards, headsets, keyboards,
mice, and LAN cards
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
A
Y
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LVC14A, SN74LVC14A
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SCAS285AC – MARCH 1993 – REVISED APRIL 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions:
SN54LVC14A................................................................ 5
6.4 Recommended Operating Conditions:
SN74LVC14A................................................................ 6
6.5 Thermal Information....................................................6
6.6 Electrical Characteristics, SN54LVC14A.................... 6
6.7 Electrical Characteristics, SN74LVC14A.................... 7
6.8 Switching Characteristics, SN54LVC14A....................8
6.9 Switching Characteristics, SN74LVC14A....................9
6.10 Operating Characteristics......................................... 9
6.11 Typical Characteristics.............................................. 9
7 Parameter Measurement Information.......................... 10
8 Detailed Description...................................................... 11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................12
9 Application and Implementation.................................. 13
9.1 Application Information............................................. 13
9.2 Typical Application.................................................... 13
10 Power Supply Recommendations..............................14
11 Layout........................................................................... 15
11.1 Layout Guidelines................................................... 15
11.2 Layout Examples.....................................................15
12 Device and Documentation Support..........................16
12.1 Documentation Support.......................................... 16
12.2 Receiving Notification of Documentation Updates..16
12.3 Support Resources................................................. 16
12.4 Trademarks............................................................. 16
12.5 Electrostatic Discharge Caution..............................16
12.6 Glossary..................................................................16
13 Mechanical, Packaging, and Orderable
Information.................................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision AB (June 2015) to Revision AC (April 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Removed the Standard CMOS Inputs section.................................................................................................. 11
• Added the CMOS Schmitt-Trigger Inputs section............................................................................................. 11
• Removed Δt/Δv specifications throughout the data sheet................................................................................ 14
Changes from Revision AA (June 2015) to Revision AB (January 2019)
Page
• Changed order of the 'Features' list ...................................................................................................................1
• Deleted "Ioff Support Live Insertion, Partial-Power-Down Mode and Back Drive protection" from Features list. 1
• Deleted Device Options table, see Mechanical, Packaging, and Orderable Information at the end of the data
sheet................................................................................................................................................................... 1
• Added VO > VCC to Output clamp current in Absolute Maximum Ratings ......................................................... 5
• Changed MAX value for Output clamp current, IOK from: –50 to: ±50 ............................................................... 5
• Changed values in the Thermal Information table to align with JEDEC standards............................................ 6
• Added Feature Description sections for Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS
Inputs, Clamp Diodes, and Over-Voltage Tolerant Inputs ................................................................................ 11
• Added Related Documentation and Receiving Notification of Documentation Updates sections.................... 16
Changes from Revision Z (January 2014) to Revision AA (June 2015)
Page
• Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table,
Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ............................................................................. 1
• Moved Tstg to Absolute Maximum Ratings table.................................................................................................5
Changes from Revision Y (October 2010) to Revision Z (January 2014)
Page
• Updated document to new TI data sheet format.................................................................................................1
• Updated Features .............................................................................................................................................. 1
2
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•
SN54LVC14A, SN74LVC14A
SCAS285AC – MARCH 1993 – REVISED APRIL 2022
Added Military Disclaimer to Features list...........................................................................................................1
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SCAS285AC – MARCH 1993 – REVISED APRIL 2022
13
3
12
4
11
5
10
6
9
7
8
VCC
6A
6Y
5A
5Y
4A
4Y
1Y
2A
2Y
3A
3Y
1
14
2
13 6A
3
12 6Y
4
11 5A
5
10 5Y
9 4A
6
7
8
Figure 5-2. RGY Package, 14-Pin VQFN (Top View)
1Y
1A
NC
VCC
6A
Figure 5-1. D, DB, DGV, NS, J, W, or PW Package,
14-Pin SOIC, SSOP, TVSOP, SO, CDIP, CFP, or
TSSOP (Top View)
VCC
14
2
4Y
1
GND
1A
1Y
2A
2Y
3A
3Y
GND
1A
5 Pin Configuration and Functions
4
2 1 20 19
18
5
3
17
6
16
7
15
8
14
9 10 11 12 13
6Y
NC
5A
NC
5Y
3Y
GND
NC
4Y
4A
2A
NC
2Y
NC
3A
Figure 5-3. FK Package, 20-Pin LCCC (Top View)
Table 5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
SOIC, SSOP, TVSOP, SO,
CDIP, CFP, TSSOP, VQFN
LCCC
1A
1
2
I
Data input
2A
3
4
I
Data input
3A
5
8
I
Data input
4A
9
13
I
Data input
5A
11
16
I
Data input
6A
13
19
I
Data input
GND
7
10
—
Ground
VCC
14
20
—
Positive supply
1Y
2
3
O
Data output
2Y
4
6
O
Data output
3Y
6
9
O
Data output
4Y
8
12
O
Data output
5Y
10
14
O
Data output
6Y
12
18
O
Data output
—
No connection
NAME
1
5
NC
—
7
11
15
17
(1)
4
I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
VI
Input
voltage(2)
–0.5
6.5
V
VO
Output voltage(2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
500
mW
150
°C
VCC
Ptot
Power dissipation
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(5)
TA = –40°C to
+125°C(4) (5)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
For the DB, DGV, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
+2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
+1000
Machine Model
(1)
(2)
UNIT
V
200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions: SN54LVC14A
See (1)
SN54LVC14A
–55 TO +125°C
VCC
Supply voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
(1)
Operating
Data retention only
MIN
MAX
2
3.6
1.5
UNIT
V
0
5.5
V
0
VCC
V
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 2.7 V
12
VCC = 3 V
24
mA
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
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6.4 Recommended Operating Conditions: SN74LVC14A
See (1)
SN74LVC14A
TA = 25°C
Operating
–40 TO +85°C –40 TO +125°C
MIN
MAX
MIN
MAX
MIN
MAX
1.65
3.6
1.65
3.6
1.65
3.6
UNIT
VCC
Supply voltage
VI
Input voltage
0
5.5
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
0
VCC
V
IOH
High-level output current
Data retention only
1.5
(1)
Low-level output current
V
1.5
VCC = 1.65 V
–4
–4
–4
VCC = 2.3 V
–8
–8
–8
VCC = 2.7 V
–12
–12
–12
VCC = 3 V
–24
–24
–24
4
4
4
VCC = 1.65 V
IOL
1.5
VCC = 2.3 V
8
8
8
VCC = 2.7 V
12
12
12
VCC = 3 V
24
24
24
mA
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.5 Thermal Information
SN74LVC14A
THERMAL METRIC(1)
D (SOIC)
DB (SSOP)
DGV (TVSOP)
NS (SO)
PW (TSSOP)
RGY (LCCC)
14 PINS
UNIT
20 PINS
RθJA
Junction-to-ambient thermal
resistance
117.6
131.8
153.5
115.7
145.9
93.8
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
78.2
83.9
75.2
72.2
73.4
106.7
°C/W
RθJB
Junction-to-board thermal resistance
71.9
79.2
86.6
74.4
87.7
69.8
°C/W
ψJT
Junction-to-top characterization
parameter
39.3
41.7
19.9
33.7
18.9
22.0
°C/W
ψJB
Junction-to-board characterization
parameter
71.6
78.6
85.9
74.1
87.1
70.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
—
—
—
—
—
49.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Electrical Characteristics, SN54LVC14A
over operating free-air temperature range (unless otherwise noted)
SN54LVC14A
PARAMETER
TEST CONDITIONS
VCC
VT+
VT–
6
Positive-going
threshold
Negative-going
threshold
UNIT
–55 TO +125°C
MIN
TYP
MAX
2.7 V
0.8
2
3V
0.9
2
3.6 V
1.1
2
2.7 V
0.4
1.4
3V
0.6
1.5
3.6 V
0.8
1.7
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V
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6.6 Electrical Characteristics, SN54LVC14A (continued)
over operating free-air temperature range (unless otherwise noted)
SN54LVC14A
PARAMETER
TEST CONDITIONS
VCC
–55 TO +125°C
MIN
ΔVT
Hysteresis
(VT+ – VT-)
IOH = –100 μA
ICC
IOL = 100 μA
ΔICC
0.3
1.1
3V
0.3
1.2
3.6 V
0.3
1.2
V
VCC – 0.2
2.7 V
2.2
II
2.4
3V
2.2
V
2.7 V to 3.6 V
0.2
2.7 V
0.4
3V
0.55
Ci
IOL = 24 mA
V
VI = 5.5 V or GND
3.6 V
±5
μA
VI = VCC or GND, IO = 0
3.6 V
10
μA
2.7 V to 3.6 V
500
μA
One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND
(1)
MAX
2.7 V
2.7 V to 3.6 V
VOL
VOH
TYP
UNIT
5(1)
3.3 V
pF
TA = 25°C
6.7 Electrical Characteristics, SN74LVC14A
over operating free-air temperature range (unless otherwise noted)
SN74LVC14A
PARAMETER
TEST
CONDITIONS
VCC
TA = 25°C
MIN
VT+
VT–
Positivegoing
threshold
Negativegoing
threshold
TYP
–40 TO +85°C
–40 TO +125°C
UNIT
MAX
MIN
MAX
MIN
MAX
1.65 V
0.4
1.3
0.4
1.3
0.4
1.3
1.95 V
0.6
1.5
0.6
1.5
0.6
1.5
2.3 V
0.8
1.7
0.8
1.7
0.8
1.7
2.5 V
0.8
1.7
0.8
1.7
0.8
1.7
2.7 V
0.8
2
0.8
2
0.8
2
3V
0.9
2
0.9
2
0.9
2
3.6 V
1.1
2
1.1
2
1.1
2
1.65 V
0.15
0.85
0.15
0.85
0.15
0.85
1.95 V
0.25
0.95
0.25
0.95
0.25
0.95
2.3 V
0.4
1.2
0.4
1.2
0.4
1.2
2.5 V
0.4
1.2
0.4
1.2
0.4
1.2
2.7 V
0.4
1.4
0.4
1.4
0.4
1.4
3V
0.6
1.5
0.6
1.5
0.6
1.5
3.6 V
0.8
1.7
0.8
1.7
0.8
1.7
V
V
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6.7 Electrical Characteristics, SN74LVC14A (continued)
over operating free-air temperature range (unless otherwise noted)
SN74LVC14A
PARAMETER
TEST
CONDITIONS
VCC
TA = 25°C
MIN
ΔVT
Hysteresis
(VT+ – VT-)
TYP
–40 TO +125°C
UNIT
MAX
MIN
MAX
MIN
MAX
1.65 V
0.1
1.15
0.1
1.15
0.1
1.15
1.95 V
0.15
1.25
0.15
1.25
0.15
1.25
2.3 V
0.25
1.3
0.25
1.3
0.25
1.3
2.5 V
0.25
1.3
0.25
1.3
0.25
1.3
2.7 V
0.3
1.1
0.3
1.1
0.3
1.1
3V
0.3
1.2
0.3
1.2
0.3
1.2
3.6 V
0.3
1.2
0.3
1.2
0.3
1.2
1.65 V to
3.6 V
IOH = –100 μA
–40 TO +85°C
VCC – 0.2
VCC – 0.2
V
VCC – 0.3
IOH = –4 mA
1.65 V
1.29
1.2
1.05
IOH = –8 mA
2.3 V
1.9
1.7
1.65
2.7 V
2.2
2.2
2.05
3V
2.4
2.4
2.25
IOH = –24 mA
3V
2.3
2.2
2
IOL = 100 μA
1.65 V to
3.6 V
0.1
0.2
IOL = 4 mA
1.65 V
0.24
0.45
0.6
IOL = 8 mA
2.3 V
0.3
0.7
0.75
IOL = 12 mA
2.7 V
0.4
0.4
0.6
IOL = 24 mA
3V
0.55
0.55
0.8
II
VI = 5.5 V or
GND
3.6 V
±1
±5
±20
μA
ICC
VI = VCC or
GND, IO = 0
3.6 V
1
10
40
μA
ΔICC
One input at
VCC – 0.6 V,
Other inputs at
VCC or GND
500
500
5000
μA
Ci
VI = VCC or GND
VOH
IOH = –12 mA
VOL
2.7 V to
3.6 V
3.3 V
V
0.3
5
V
pF
6.8 Switching Characteristics, SN54LVC14A
over operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
SN54LVC14A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
–55 TO +125°C
MIN
tpd
8
A
Y
2.7 V
3.3 V ± 0.3 V
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7.5
1
UNIT
MAX
6.4
ns
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6.9 Switching Characteristics, SN74LVC14A
over operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
SN74LVC14A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
MIN
tpd
A
Y
tsk(o)
–40 TO +85°C
TYP
MAX
MIN
–40 TO
+125°C
UNIT
MAX
MIN
MAX
1.8 V ± 0.15 V
1
5
10.5
1
11
1
13
2.5 V ± 0.2 V
1
3.4
7.3
1
7.8
1
10
2.7 V
1
3.6
7.3
1
7.5
1
9.5
3.3 V ± 0.3 V
1
3.2
6.2
1
6.4
1
8
3.3 V ± 0.3 V
1
1
1.5
ns
ns
6.10 Operating Characteristics
TA = 25°C
Cpd
PARAMETER
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
Power dissipation capacitance
f = 10 MHz
11
12
15
UNIT
pF
6.11 Typical Characteristics
Power Dissipation Capacitance (C pd)
16
15
14
13
12
11
10
1.5
1.7
1.9
2.1 2.3 2.5 2.7 2.9 3.1
Power Suppoly Voltage (VCC)
3.3
3.5
D001
Figure 6-1. Power Dissipation Capacitance vs. Power Supply Voltage
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + VD
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH - VD
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
The SN54LVC14A hex Schmitt-trigger inverter is designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVC14A hex Schmitt-trigger inverter is designed for 1.65-V to 3.6-V VCC operation.
The devices contain six independent inverters and perform the Boolean function Y = A.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V or 5-V system environment.
8.2 Functional Block Diagram
A
Y
Figure 8-1. Logic Diagram, Each Inverter (Positive Logic)
8.3 Feature Description
8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings
section must be followed at all times.
8.3.2 CMOS Schmitt-Trigger Inputs
This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are
typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table
from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the
Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics
table, using Ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics
table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional
information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
8.3.3 Clamp Diodes
The inputs to this device have negative clamping diodes. The outputs to this device have both positive and
negative clamping diodes as shown in Figure 8-2.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input negative-voltage and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
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Device
VCC
+IOK
Logic
Input
-IIK
Output
-IOK
GND
Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Over-Voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Absolute Maximum Ratings table.
8.4 Device Functional Modes
Table 8-1 lists the functional modes for the SN54LVC14A and SN74LVC14A devices.
Table 8-1. Function Table (Each Inverter)
12
INPUT
A
OUTPUT
Y
H
L
L
H
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
Physically interactive interface elements like push buttons or rotary knobs offer simple and easy ways to interact
with an electronic system. Many of these physical interface elements often have issues with bouncing, or where
the physical conductive contact can connect and disconnect multiple times during a button push or release. This
bouncing can cause one or more faulty transient signals to be passed during this transitional period. These faulty
signals can be observed in many common applications: for example, a television remote with bouncing error can
adjust the TV channel multiple times despite the button being pushed only once. To mitigate these faulty signals,
use a Schmitt-trigger, or a device with hysteresis, to remove these faulty signals. Hysteresis allows a device to
remember its history, and in this case, the LVC14A uses this memory to debounce the physical element's signal,
or filter the faulty transient signals and pass only the valid signal each time the element is used. In this example,
we show a push button signal passed through an LVC14A that is debounced and inverted to the MCU for push
detection.
9.2 Typical Application
The signal effects of the debounce circuit can be seen when comparing Figure 9-2 and Figure 9-3. In Figure 9-2,
the input is a very poor quality signal due to the error in the physical push button. If the MCU attempts to sample
this input to detect a push, there is high probability that multiple push events will be falsely detected. Once
the debounce circuit has been implemented, the input is cleaned up, and the MCU can perform push detection
without any error, as seen in Figure 9-3.
VCC = 3.3 V
GND
VCC
LVC14A
Push Button
1A
(x6)
1Y
MCU
(MSP43x)
Copyright © 2017, Texas Instruments Incorporated
Figure 9-1. Debouncer Application Diagram
9.2.1 Design Requirements
The SN74LVC14A device uses CMOS technology and has balanced output drive. Take care to avoid bus
contention because it can drive currents that would exceed maximum limits.
The SN74LVC14A allows for performing logical Boolean functions with hysteresis using digital signals. All input
signals should remain as close as possible to either 0 V or VCC for optimal operation.
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9.2.2 Detailed Design Procedure
1. Recommended input conditions:
• For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions:
SN74LVC14A table.
• Inputs and outputs are overvoltage tolerant and can therefore go as high as 3.6 V at any valid VCC.
2. Recommended output conditions:
• Load currents should not exceed ±50 mA.
3. Frequency selection criterion:
• Added trace resistance and capacitance can reduce maximum frequency capability; follow the layout
practices listed in the Layout section
9.2.3 Application Curves
VBUT
VBUT
t
t
Figure 9-2. Input Response Without Debounce
Circuit
Figure 9-3. Input Response With Debounce Circuit
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Absolute Maximum Ratings table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a
single supply, a 0.1-µF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-µF or
0.022-µF capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices
with dual supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is
recommended for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in
parallel. Capacitors with values of 0.1 µF and 1 µF are commonly used in parallel. The bypass capacitor should
be installed as close to the power terminal as possible for best results.
14
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11 Layout
11.1 Layout Guidelines
When using multiple-bit logic devices, inputs must never float.
In many cases, functions (or parts of functions) of digital logic devices are unused, for example, when only
two inputs of a triple-input AND gate are used or when only 3 of the 4 buffer gates are used. Such input pins
must not be left unconnected, because the undefined voltages at the outside connections result in undefined
operational states. Figure 11-1 specifies the rules that must be observed under all circumstances. All unused
inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic
level that must be applied to any particular unused input depends on the function of the device. Generally they
are tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float
outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it disables the output section
of the part when asserted, which does not disable the input section of the I/Os. Therefore, the I/Os cannot float
when disabled.
11.2 Layout Examples
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 11-1. Layout Diagrams
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9761501Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629761501Q2A
SNJ54LVC
14AFK
5962-9761501QCA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9761501QC
A
SNJ54LVC14AJ
5962-9761501QDA
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9761501QD
A
SNJ54LVC14AW
5962-9761501V2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629761501V2A
SNV54LVC
14AFK
5962-9761501VCA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9761501VC
A
SNV54LVC14AJ
5962-9761501VDA
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9761501VD
A
SNV54LVC14AW
SN74LVC14AD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC14A
Samples
SN74LVC14ADBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC14A
Samples
SN74LVC14ADBRE4
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC14A
Samples
SN74LVC14ADE4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC14A
Samples
SN74LVC14ADG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC14A
Samples
SN74LVC14ADGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC14A
Samples
SN74LVC14ADR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LVC14A
Samples
SN74LVC14ADRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC14A
Samples
SN74LVC14ADRG3
ACTIVE
SOIC
D
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LVC14A
Samples
Addendum-Page 1
Samples
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Jun-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC14ADRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC14A
Samples
SN74LVC14ADT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC14A
Samples
SN74LVC14ANSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC14A
Samples
SN74LVC14APW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC14A
Samples
SN74LVC14APWG4
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC14A
Samples
SN74LVC14APWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LC14A
Samples
SN74LVC14APWRE4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC14A
Samples
SN74LVC14APWRG3
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LC14A
Samples
SN74LVC14APWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC14A
Samples
SN74LVC14APWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC14A
Samples
SN74LVC14APWTG4
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC14A
Samples
SN74LVC14ARGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC14A
Samples
SN74LVC14ARGYRG4
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC14A
Samples
SNJ54LVC14AFK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629761501Q2A
SNJ54LVC
14AFK
SNJ54LVC14AJ
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9761501QC
A
SNJ54LVC14AJ
SNJ54LVC14AW
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9761501QD
A
SNJ54LVC14AW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 2
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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