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SN74LVC16373A
SCAS755B – DECEMBER 2003 – REVISED JUNE 2014
SN74LVC16373A 16-Bit Transparent D-Type Latch With 3-State Outputs
1 Features
2 Applications
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1
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Member of the Texas Instruments
Widebus™ Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.2 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Live-Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Supports Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V VCC)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
Servers
PCs and Notebooks
Network Switches
Wearable Health and Fitness Devices
Telecom Infrastructures
Electronic Points of Sale
3 Description
The SN74LVC16373A device is a 16-bit transparent
D-type latch which is designed for 1.65-V to 3.6-V
VCC operation.
Device Information(1)
PART NUMBER
SN74LVC16373A
PACKAGE
BODY SIZE (NOM)
TSSOP (48)
12.50 mm × 6.10 mm
TVSOP (48)
9.70 mm × 4.40 mm
SSOP (48)
15.80 mm × 7.49 mm
BGA MICROSTAR
JUNIOR (56)
7.00 mm × 4.50 mm
BGA MICROSTAR
JUNIOR (54)
8.00 mm × 5.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
1OE
1LE
1
2OE
48
2LE
C1
1D1
47
1D
To Seven Other Channels
2
24
25
C1
1Q1
2D1
36
1D
13
2Q1
To Seven Other Channels
Pin numbers shown are for the DGG, DGV, and DL packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC16373A
SCAS755B – DECEMBER 2003 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
6
6
7
7
8
8
8
8
9
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
9
Detailed Description ............................................ 11
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
11
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ............................................... 12
11 Power Supply Recommendations ..................... 13
12 Layout................................................................... 13
12.1 Layout Guidelines ................................................. 13
12.2 Layout Example .................................................... 13
13 Device and Documentation Support ................. 14
13.1 Trademarks ........................................................... 14
13.2 Electrostatic Discharge Caution ............................ 14
13.3 Glossary ................................................................ 14
14 Mechanical, Packaging, and Orderable
Information ........................................................... 14
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2005) to Revision B
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Device Information table. ............................................................................................................................................ 1
•
Added Handling Ratings table. .............................................................................................................................................. 6
•
Changed MAX ambient temperature to 125°C. ..................................................................................................................... 7
•
Added Thermal Information table. .......................................................................................................................................... 7
•
Added Typical Characteristics. .............................................................................................................................................. 9
2
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SCAS755B – DECEMBER 2003 – REVISED JUNE 2014
6 Pin Configuration and Functions
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
Pin Functions
PIN
I/O
DESCRIPTION
OE
I
Output Enable
1Q1
O
1Q1 Output
3
1Q2
O
1Q2 Output
4
GND
—
Ground Pin
5
1Q3
O
1Q3 Output
6
1Q4
O
1Q4 Output
7
VCC
—
Power Pin
8
1Q5
O
1Q5 Output
9
1Q6
O
1Q6 Output
10
GND
—
Ground Pin
11
1Q7
O
1Q7 Output
12
1Q8
O
1Q8 Output
13
2Q1
O
2Q1 Output
14
2Q2
O
2Q2 Output
15
GND
—
Ground Pin
16
2Q3
O
2Q3 Output
17
2Q4
O
2Q4 Output
18
VCC
—
Power Pin
19
2Q5
O
2Q5 Output
20
2Q6
O
2Q6 Output
NO.
NAME
1
2
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SCAS755B – DECEMBER 2003 – REVISED JUNE 2014
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
GND
—
Ground Pin
2Q7
O
2Q7 Output
23
2Q8
O
2Q8 Output
24
2OE
O
Output Enable 2
25
2LE
I
Latch Enable 2
26
2D8
I
2D8 Input
27
2D7
I
2D7 Input
28
GND
—
29
2D6
I
2D6 Input
30
2D5
I
2D5 Input
31
VCC
—
Power Pin
32
2D4
I
2D4 Input
33
2D3
I
2D3 Input
34
GND
—
35
2D2
I
2D2 Input
36
2D1
I
2D1 Input
37
1D8
I
1D8 Input
38
1D7
I
1D7 Input
39
GND
—
40
1D6
I
1D6 Input
41
1D5
I
1D5 Input
42
VCC
—
Power Pin
43
1D4
I
1D4 Input
44
1D3
I
1D3 Input
45
GND
—
46
1D2
I
1D2 Input
47
1D1
I
1D1 Input
48
1LE
I
Latch Enable 1
NO.
NAME
21
22
4
Ground Pin
Ground Pin
Ground Pin
Ground Pin
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SCAS755B – DECEMBER 2003 – REVISED JUNE 2014
GQL OR ZQL PACKAGE
(TOP VIEW)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
Pin Assignments (1) (56-Ball GQL or ZQL Package)
1
(1)
2
3
4
5
6
A
1OE
NC
NC
NC
NC
1LE
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
VCC
VCC
1D3
1D4
D
1Q6
1Q5
GND
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
2D4
2D3
H
2Q5
2Q6
VCC
VCC
2D6
2D5
J
2Q7
2Q8
GND
GND
2D8
2D7
K
2OE
NC
NC
NC
NC
2LE
GND
NC – No internal connection
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
Pin Assignments (1) (54-Ball GRD or ZRD Package)
(1)
1
2
3
4
5
6
A
1Q1
NC
1OE
1LE
NC
1D1
B
1Q3
1Q2
NC
NC
1D2
1D3
C
1Q5
1Q4
VCC
VCC
1D4
1D5
D
1Q7
1Q6
GND
GND
1D6
1D7
E
2Q1
1Q8
GND
GND
1D8
2D1
F
2Q3
2Q2
GND
GND
2D2
2D3
G
2Q5
2Q4
VCC
VCC
2D4
2D5
H
2Q7
2Q6
NC
NC
2D6
2D7
J
2Q8
NC
2OE
2LE
NC
2D8
NC – No internal connection
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
6
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
Storage temperature range
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCAS755B – DECEMBER 2003 – REVISED JUNE 2014
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
MIN
MAX
1.65
3.6
Low-level input voltage
VI
Input voltage
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VO
Output voltage
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition rise and fall rate
TA
Operating free-air temperature
(1)
V
0.8
0
5.5
High or low state
0
VCC
High-impedance state
0
5.5
VCC = 1.65 V
IOH
V
1.5
VCC = 1.65 V to 1.95 V
VIL
UNIT
V
V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
4
VCC = 2.3 V
8
VCC = 2.7 V
12
VCC = 3 V
24
–40
mA
mA
10
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
THERMAL METRIC (1)
DL
48 PINS
RθJA
Junction-to-ambient thermal resistance
68.4
RθJC(top)
Junction-to-case (top) thermal resistance
34.7
RθJB
Junction-to-board thermal resistance
41.0
ψJT
Junction-to-top characterization parameter
12.3
ψJB
Junction-to-board characterization parameter
40.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 μA
VOH
1.65 V to 3.6 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.7
2.7 V
2.2
UNIT
V
3V
2.4
IOH = –24 mA
3V
2.2
IOL = 100 μA
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
3V
0.55
IOL = 24 mA
V
±5
μA
Ioff
VI or VO = 5.5 V
0
±10
μA
IOZ
VO = 0 to 5.5 V
3.6 V
±10
μA
II
ICC
ΔICC
(1)
(2)
TYP (1) MAX
VCC – 0.2
IOH = –4 mA
IOH = –12 mA
VOL
MIN
VI = 0 to 5.5 V
VI = VCC or GND
IO = 0
3.6 V ≤ VI ≤ 5.5 V (2)
3.6 V
20
3.6 V
One input at VCC – 0.6 V, Other inputs at VCC or GND
20
2.7 V to 3.6 V
500
μA
μA
Ci
VI = VCC or GND
3.3 V
5
pF
Co
VO = VCC or GND
3.3 V
6.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This applies in the disabled state only.
7.6 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 1.8 V ± 0.15 V
MIN
VCC = 2.5 V ± 0.2 V
MAX
MIN
VCC = 2.7 V
MAX
MIN
VCC = 3.3 V ± 0.3 V
MAX
MIN
MAX
UNIT
tw
Pulse duration, LE high
3.3
3.3
3.3
3.3
ns
tsu
Setup time, data before LE↓
1.6
1.2
1.7
1.7
ns
th
Hold time, data after LE↓
1
1.1
1.2
1.2
ns
7.7 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
FROM
(INPUT)
D
LE
TO
(OUTPUT)
Q
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.5
6.4
1
4.2
1
4.9
1.6
4.2
1.5
7.1
1
4.8
1
5.3
2.1
4.6
UNIT
ns
ten
OE
Q
1.5
6.7
1
4.7
1
5.7
1.3
4.7
ns
tdis
OE
Q
1.5
8.4
1
5
1
6.3
2.5
5.9
ns
7.8 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
8
Power dissipation capacitance
per latch
Outputs enabled
Outputs disabled
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
32
35
39
4
4
6
f = 10 MHz
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UNIT
pF
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7.9 Typical Characteristics
6
8
TPD in ns
7
5
6
TPD - ns
TPD - ns
4
3
5
4
3
2
2
1
1
TPD in ns
0
-100
0
-50
0
50
Temperature (qC)
100
150
0
0.5
D001
Figure 1. SN74LVC16373A
LE to Q Across Temperature 3.3-V VCC
1
1.5
2
VCC - V
2.5
3
3.5
D002
Figure 2. SN74LVC16373A LE to Q TDP
VCC vs TPD at 25°C
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
10
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9 Detailed Description
9.1 Overview
The SN74LVC16373A device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latchenable (LE) input high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched
at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components. OE does not affect internal operations of the latch. Old data can be
retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from
either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system
environment. To ensure the high-impedance state during power up or power down, OE should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
9.2 Functional Block Diagram
1OE
1LE
1
2OE
48
2LE
C1
1D1
47
2
1D
24
25
C1
1Q1
2D1
36
1D
To Seven Other Channels
13
2Q1
To Seven Other Channels
Pin numbers shown are for the DGG, DGV, and DL packages.
Figure 4. Logic Diagram (Positive Logic)
9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 1.65 V to 3.6 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V
9.4 Device Functional Modes
Function Table
(Each Latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
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10 Application and Implementation
10.1 Application Information
The SN74LVC16373A device is a high drive CMOS device that can be used for a multitude of bus-interface type
applications where the data needs to be retained or latched. It can produce 24 mA of drive current at 3.3 V.
Therefore, this device is ideal for driving multiple outputs and for high speed applications up to 100 Mhz. The
inputs are 5.5 V tolerant allowing it to translate down to VCC.
10.2 Typical Application
Regulated 3.6 V
OE
Vcc
LE
1D
1Q
uC
System Logic
uC or
System Logic
8D
LEDs
8Q
GND
Figure 5. Typical Application Diagram
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads; therefore, routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 50 mA per output and 100 mA total for the part.
– Outputs should not be pulled above VCC.
12
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Typical Application (continued)
10.2.3 Application Curves
3
ICC 1.8 V
ICC 2.5 V
ICC 3.3 V
Frequency - MHz
2.5
2
1.5
1
0.5
0
0
10
20
30
ICC - V
40
50
60
D003
Figure 6. ICC vs Frequency
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a
1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 7 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
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13 Device and Documentation Support
13.1 Trademarks
Widebus is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
74LVC16373ADGGRG4
ACTIVE
TSSOP
DGG
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC16373A
74LVC16373ADGVRE4
ACTIVE
TVSOP
DGV
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LD373A
SN74LVC16373ADGGR
ACTIVE
TSSOP
DGG
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC16373A
SN74LVC16373ADGVR
ACTIVE
TVSOP
DGV
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LD373A
SN74LVC16373ADL
ACTIVE
SSOP
DL
48
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC16373A
SN74LVC16373ADLG4
ACTIVE
SSOP
DL
48
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC16373A
SN74LVC16373ADLR
ACTIVE
SSOP
DL
48
1000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC16373A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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