www.ti.com
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
FEATURES
•
•
•
•
•
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Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
DESCRIPTION
This 16-bit transparent D-type latch is designed for
2.7-V to 3.6-V VCC operation.
The SN74LVC16373 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. It can be used as
two 8-bit latches or one 16-bit latch. When the
latch-enable (LE) input is high, the Q outputs follow
the data (D) inputs. When LE is taken low, the Q
outputs are latched at the levels set up at the D
inputs.
SCAS315B – NOVEMBER 1993 – REVISED MARCH 2005
DGG OR DL PACKAGE
(TOP VIEW)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVC16373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2005, Texas Instruments Incorporated
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCAS315B – NOVEMBER 1993 – REVISED MARCH 2005
FUNCTION TABLE
(EACH 8-BIT SECTION)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
LOGIC SYMBOL(1)
1OE
1LE
2OE
2LE
1
48
24
25
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1EN
C3
1LE
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
47
C1
C4
3D
46
2
1
3
44
5
43
6
41
8
40
9
38
11
37
12
36
35
4D
13
2
14
33
16
32
17
30
19
29
20
27
22
26
23
47
2
1Q1
1D
1Q1
1Q2
1Q3
1Q4
To Seven Other Channels
1Q5
1Q6
1Q7
2OE
24
1Q8
2Q1
2LE
25
2Q2
2Q3
2Q4
C1
2D1
36
1D
2Q5
2Q6
2Q7
2Q8
(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2
48
2EN
1D1
1D1
1
To Seven Other Channels
13
2Q1
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCAS315B – NOVEMBER 1993 – REVISED MARCH 2005
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
4.6
V
–0.5
VCC + 0.5
range (2) (3)
UNIT
VO
Output voltage
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±50
mA
IO
Continuous output current
VO = 0 to VCC
±50
mA
±100
mA
Continuous current through VCC or GND
Maximum power dissipation at TA = 55°C (in still air) (4)
Tstg
(1)
(2)
(3)
(4)
DGG package
0.85
DL package
Storage temperature range
V
W
1.2
–65
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 4.6 V maximum.
The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For
more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002B.
Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
VI
Input voltage
VO
Output voltage
MIN
MAX
2.7
3.6
2
UNIT
V
V
0.8
V
0
VCC
V
0
VCC
V
VCC = 2.7 V
–12
VCC = 3 V
–24
IOH
High-level output current
IOL
Low-level output current
∆t/∆V
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
–40
85
°C
(1)
VCC = 2.7 V
12
VCC = 3 V
24
mA
mA
Unused control inputs must be held high or low to prevent them from floating.
3
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCAS315B – NOVEMBER 1993 – REVISED MARCH 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC (1)
TEST CONDITIONS
IOH = –100 µA
VOH
MIN to MAX
II
2.2
3V
2.4
IOH = –24 mA
3V
2
IOL = 100 µA
MIN to MAX
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3V
0.55
VI = VCC or GND
II(hold)
Data inputs
V
0.2
±5
3.6 V
VI = 0.8 V
75
3V
VI = 2 V
UNIT
VCC – 0.2
2.7 V
IOH = –12 mA
VOL
MIN TYP (2) MAX
V
µA
µA
–75
3.6 V
±10
µA
3.6 V
40
µA
500
µA
IOZ
VO = VCC or GND
ICC
VI = VCC or GND,
IO = 0
∆ICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
3.3 V
3.5
pF
Co
VO = VCC or GND
3.3 V
7
pF
(1)
(2)
3 V to 3.6 V
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
All typical values are at VCC = 3.3 V, TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN MAX
UNIT
MIN MAX
tw
Pulse duration, LE high
4
4
ns
tsu
Setup time, data before LE↓
2
2
ns
th
Hold time, data after LE↓
2
2
ns
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see
Figure 1)
PARAMETER
tpd
FROM
(INPUT)
D
LE
TO
(OUTPUT)
Q
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN MAX
UNIT
MIN MAX
1.5
7
8
2
8
9
ns
ten
OE
Q
1.5
8
9
ns
tdis
OE
Q
1.5
7
8
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance per latch
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 50 pF, f = 10 MHz
TYP
20
4
UNIT
pF
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCAS315B – NOVEMBER 1993 – REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT FOR OUTPUTS
1.5 V
Timing Input
0V
tw
tsu
2.7 V
1.5 V
Input
1.5 V
th
2.7 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
1.5 V
Input
1.5 V
0V
tPHL
tPLH
Output
1.5 V
VOL
tPHL
VOH
Output
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPLZ
3V
1.5 V
tPZH
1.5 V
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
VOH
1.5 V
2.7 V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform
2 is for an output with internal conditions such that the ouput is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 , tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
5
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
74LVC16373DGGRE4
ACTIVE
TSSOP
DGG
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC16373
SN74LVC16373DGGR
ACTIVE
TSSOP
DGG
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC16373
SN74LVC16373DL
ACTIVE
SSOP
DL
48
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC16373
SN74LVC16373DLR
ACTIVE
SSOP
DL
48
1000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC16373
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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