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SN74LVC16T245GQLR

SN74LVC16T245GQLR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    JRBGA56

  • 描述:

    IC BUS TRANSCVR 16BIT 56BGA

  • 数据手册
  • 价格&库存
SN74LVC16T245GQLR 数据手册
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN74LVC16T245 SCES636B – AUGUST 2005 – REVISED APRIL 2015 SN74LVC16T245 16-bit Dual-Supply Bus Transceiver With Configurable Level-Shifting / Voltage Translation and Tri-State Outputs 1 Features 3 Description • This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. 1 • • • • • • Control Inputs VIH/VIL Levels are Referenced to VCCA Voltage VCC Isolation Feature – If Either VCC Input is at GND, Both Ports are in the High-Impedance State Overvoltage-Tolerant Inputs and Outputs Allow Mixed Voltage-Mode Data Communications Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2 Applications • • • • Personal Electronics Industrial Enterprise Telecom The SN74LVC16T245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. Device Information(1) PART NUMBER SN74LVC16T245 PACKAGE BODY SIZE (NOM) TSSOP (48) 12.50 mm × 6.10 mm TVSOP (48) 9.70 mm × 4.40 mm SSOP (48) 15.88 mm × 7.49 mm BGA MICROSTAR 7.00 mm × 4.50 mm JUNIOR (56) (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 To Seven Other Channels 24 2OE 36 13 1B1 2B1 To Seven Other Channels 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC16T245 SCES636B – AUGUST 2005 – REVISED APRIL 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 8 1 1 1 2 3 4 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions ...................... 7 Thermal Information .................................................. 8 Electrical Characteristics........................................... 8 Switching Characteristics: VCCA = 1.8 V ±0.15 V...... 9 Switching Characteristics: VCCA = 2.5 V ±0.2 V........ 9 Switching Characteristics: VCCA = 3.3 V ±0.3 V...... 10 Switching Characteristics: VCCA = 5 V ±0.5 V......... 10 Operating Characteristics...................................... 10 Typical Characteristics ......................................... 11 Parameter Measurement Information ................ 12 9 Detailed Description ............................................ 13 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 13 13 13 13 10 Application and Implementation........................ 15 10.1 Application Information.......................................... 15 10.2 Typical Application ............................................... 16 11 Power Supply Recommendations ..................... 18 12 Layout................................................................... 18 12.1 Layout Guidelines ................................................. 18 12.2 Layout Example .................................................... 19 13 Device and Documentation Support ................. 20 13.1 13.2 13.3 13.4 Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 14 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History Changes from Revision A (October 2005) to Revision B • 2 Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 SN74LVC16T245 www.ti.com SCES636B – AUGUST 2005 – REVISED APRIL 2015 5 Description (continued) The SN74LVC16T245 control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 3 SN74LVC16T245 SCES636B – AUGUST 2005 – REVISED APRIL 2015 www.ti.com 6 Pin Configuration and Functions DGG and DGV Packages 48-Pin TSSOP and TVSOP (Top View) 1DIR 1B1 1B2 GND 1B3 1B4 VCCB 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCCB 2B5 2B6 GND 2B7 2B8 2DIR 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 GQL and ZQL Packages 56-Pin BGA (Top View) 1 1OE 1A1 1A2 GND 1A3 1A4 VCCA 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCCA 2A5 2A6 GND 2A7 2A8 2OE 2 3 4 5 6 A B C D E F G H J K Pin Functions PIN NAME I/O DESCRIPTION DGG / DGV GQL / ZQL 1A1 47 B5 I/O Input/Output. Referenced to VCCA 1A2 46 B6 I/O Input/Output. Referenced to VCCA 1A3 44 C5 I/O Input/Output. Referenced to VCCA 1A4 43 C6 I/O Input/Output. Referenced to VCCA 1A5 41 D5 I/O Input/Output. Referenced to VCCA 1A6 40 D6 I/O Input/Output. Referenced to VCCA 1A7 38 E5 I/O Input/Output. Referenced to VCCA 1A8 37 E6 I/O Input/Output. Referenced to VCCA 1B1 2 B2 I/O Input/Output. Referenced to VCCB 1B2 3 B1 I/O Input/Output. Referenced to VCCB 1B3 5 C2 I/O Input/Output. Referenced to VCCB 1B4 6 C1 I/O Input/Output. Referenced to VCCB 1B5 8 D2 I/O Input/Output. Referenced to VCCB 1B6 9 D1 I/O Input/Output. Referenced to VCCB 1B7 11 E2 I/O Input/Output. Referenced to VCCB 1B8 12 E1 I/O Input/Output. Referenced to VCCB 1DIR 1 A1 I 4 Direction-control signal Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 SN74LVC16T245 www.ti.com SCES636B – AUGUST 2005 – REVISED APRIL 2015 Pin Functions (continued) PIN NAME I/O DESCRIPTION DGG / DGV GQL / ZQL 1OE 48 A6 I 2A1 36 F6 I/O Input/Output. Referenced to VCCA 2A2 35 F5 I/O Input/Output. Referenced to VCCA 2A3 33 G6 I/O Input/Output. Referenced to VCCA 2A4 32 G5 I/O Input/Output. Referenced to VCCA 2A5 30 H6 I/O Input/Output. Referenced to VCCA 2A6 29 H5 I/O Input/Output. Referenced to VCCA 2A7 27 J6 I/O Input/Output. Referenced to VCCA 2A8 26 J5 I/O Input/Output. Referenced to VCCA 2B1 13 F1 I/O Input/Output. Referenced to VCCB 2B2 14 F2 I/O Input/Output. Referenced to VCCB 2B3 16 G1 I/O Input/Output. Referenced to VCCB 2B4 17 G2 I/O Input/Output. Referenced to VCCB 2B5 19 H1 I/O Input/Output. Referenced to VCCB 2B6 20 H2 I/O Input/Output. Referenced to VCCB 2B7 22 J1 I/O Input/Output. Referenced to VCCB 2B8 23 J2 I/O Input/Output. Referenced to VCCB 2DIR 24 K1 I Direction-control signal 2OE 25 K6 I Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State mode. Referenced to VCCA 4 10 GND B3 B4 D3 15 D4 21 G3 28 G4 34 J3 45 Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State mode. Referenced to VCCA — Ground J4 A2 A3 A4 NC (1) — A5 K2 — K3 K4 K5 VCCA VCCB (1) 31 C4 42 H4 7 C3 18 H3 — A-port supply. 1.65 V ≤ VCCA≤ 5.5 V — B-port supply. 1.65 V ≤ VCCB≤ 5.5 V NC – No internal connection Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 5 SN74LVC16T245 SCES636B – AUGUST 2005 – REVISED APRIL 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT –0.5 6.5 V I/O ports (A port) –0.5 6.5 I/O ports (B port) –0.5 6.5 Control inputs –0.5 6.5 A port –0.5 6.5 B port –0.5 6.5 A port –0.5 VCCA + 0.5 B port –0.5 VCCB + 0.5 VCCA VCCB Supply voltage VI Input voltage (2) VO Voltage applied to any output in the high-impedance or power-off state (2) VO Voltage applied to any output in the high or low state (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through each VCCA, VCCB, and GND ±100 mA (3) V V V TJ Junction temperature -40 150 °C Tstg Storage temperature –65 150 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input (VI ) and output (VO) negative-voltage ratings may be exceeded if the input and output current ratings are observed. The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed. 7.2 ESD Ratings VALUE V(ESD) (1) (2) 6 Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1000 Machine model (A115-A) ±200 UNIT V JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 SN74LVC16T245 www.ti.com SCES636B – AUGUST 2005 – REVISED APRIL 2015 7.3 Recommended Operating Conditions See (1) (2) (3) (4) VCCI VCCA VCCB VCCO Supply voltage 1.65 V to 1.95 V High-level input voltage VIH MAX 1.65 5.5 1.65 5.5 1.7 3 V to 3.6 V 4.5 V to 5.5 V Low-level input voltage Data inputs (5) VCCI × 0.7 VCCI × 0.35 2.3 V to 2.7 V 0.7 3 V to 3.6 V 0.8 4.5 V to 5.5 V VIH Control inputs (referenced to VCCA) (6) VCCA × 0.65 2.3 V to 2.7 V 1.7 3 V to 3.6 V V 2 4.5 V to 5.5 V VCCA × 0.7 1.65 V to 1.95 V VCCA × 0.35 2.3 V to 2.7 V 0.7 3 V to 3.6 V 0.8 VIL Low-level input voltage Control inputs (referenced to VCCA) (6) VI Input voltage Control inputs 0 5.5 Input/output voltage Active state 0 VCCO Tri-State 0 5.5 4.5 V to 5.5 V VI/O High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature Data inputs (4) (5) (6) V V –4 2.3 V to 2.7 V –8 3 V to 3.6 V –24 4.5 V to 5.5 V –32 1.65 V to 1.95 V 4 2.3 V to 2.7 V 8 3 V to 3.6 V 24 4.5 V to 5.5 V 32 1.65 V to 1.95 V 20 2.3 V to 2.7 V 20 3 V to 3.6 V 10 4.5 V to 5.5 V (1) (2) (3) V VCCA × 0.3 1.65 V to 1.95 V IOH V VCCI × 0.3 1.65 V to 1.95 V High-level input voltage V V 2 1.65 V to 1.95 V VIL UNIT VCCI × 0.65 2.3 V to 2.7 V Data inputs (5) MIN mA mA ns/V 5 –40 85 °C VCCI is the VCC associated with the input port. VCCO is the VCC associated with the output port. All unused or driven (floating) data inputs (I/Os) of the device must be held at logic HIGH or LOW (preferably VCCI or GND) to ensure proper device operation and minimize power. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. All unused data inputs of the device must be held at VCCA or GND to ensure proper device operation. For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V. For VCCA values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 7 SN74LVC16T245 SCES636B – AUGUST 2005 – REVISED APRIL 2015 www.ti.com 7.4 Thermal Information SN74LVC16T245 THERMAL METRIC RθJA (1) DGG (TSSOP) DGV (TVSOP) GQL / ZQL (BGA) 48 PINS 48 PINS 48 PINS 56 PINS UNIT 92.9 60 82.5 64.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.5 13.9 34.2 16.6 °C/W RθJB Junction-to-board thermal resistance 35.5 27.1 45.1 30.8 °C/W ψJT Junction-to-top characterization parameter 8.1 0.5 2.7 0.9 °C/W ψJB Junction-to-board characterization parameter 34.9 26.8 44.6 64.6 °C/W (1) Junction-to-ambient thermal resistance DL (SSOP) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) (1) PARAMETER VOH VOL TEST CONDITIONS TA = –40°C to 85°C MAX MIN MAX 1.65 V to 4.5 V 1.65 V to 4.5 V VI = VIH 1.65 V 1.65 V 1.2 IOH = –8 mA, VI = VIH 2.3 V 2.3 V 1.9 IOH = –24 mA, VI = VIH 3V 3V 2.4 IOH = –32 mA, VI = VIH 4.5 V 4.5 V 3.8 IOL = 100 μA, VI = VIL 1.65 V to 4.5 V 1.65 V to 4.5 V 0.1 IOL = 4 mA, VI = VIL 1.65 V 1.65 V 0.45 IOL = 8 mA, VI = VIL 2.3 V 2.3 V 0.3 IOL = 24 mA, VI = VIL 3V 3V 0.55 IOL = 32 mA, VI = VIL 4.5 V 4.5 V 0.55 1.65 V to 5.5 V 1.65 V to 5.5 V ±1 ±2 Ioff A or B port VI or VO = 0 to 5.5 V IOZ A or B port VO = VCCO or GND, OE = VIH VI = VCCI or GND, IO = 0 ICCB VI = VCCI or GND, IO = 0 ICCA + ICCB VI = VCCI or GND, IO = 0 A port One A port at VCCA – 0.6 V, DIR at VCCA, B port = open DIR DIR at VCCA – 0.6 V, B port = open, A port at VCCA or GND ΔICCB B port One B port at VCCB – 0.6 V, DIR at GND, A port = open Ci Control inputs VI = VCCA or GND 8 TYP VI = VIH VI = VCCA or GND (1) (2) TA = 25°C MIN IOH = –4 mA, Control inputs ΔICCA VCCB IOH = –100 μA, II ICCA VCCA (2) UNIT VCCO – 0.1 V 0V 0 to 5.5 V ±1 ±2 0 to 5.5 V 0V ±1 ±2 1.65 V to 5.5 V 1.65 V to 5.5 V ±1 ±2 1.65 V to 5.5 V 1.65 V to 5.5 V 20 5V 0V 20 0V 5V –2 1.65 V to 5.5 V 1.65 V to 5.5 V 20 5V 0V –2 0V 5V 20 1.65 V to 5.5 V 1.65 V to 5.5 V 30 V μA μA μA μA μA μA 50 3 V to 5.5 V μA 3 V to 5.5 V 50 3 V to 5.5 V 3 V to 5.5 V 3.3 V 3.3 V 4 50 μA 5 pF VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 SN74LVC16T245 www.ti.com SCES636B – AUGUST 2005 – REVISED APRIL 2015 Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER A or B port Cio TEST CONDITIONS VO = VCCA/B or GND VCCA VCCB 3.3 V 3.3 V TA = 25°C MIN TYP TA = –40°C to 85°C MAX MIN MAX 8.5 UNIT 10 pF 7.6 Switching Characteristics: VCCA = 1.8 V ±0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH tPZL tPZH tPZL FROM (INPUT) TO (OUTPUT) A VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX B 1.7 21.9 1.3 9.2 1 7.4 0.8 7.1 ns B A 0.9 23.8 0.8 23.6 0.7 23.4 0.7 23.4 ns OE A 1.6 29.6 1.5 29.4 1.5 29.3 1.4 29.2 ns OE B 2.4 32.2 1.9 13.1 1.7 12 1.3 10.3 ns OE A 0.4 24 0.4 23.8 0.4 23.7 0.4 23.7 ns OE B 1.8 32 1.6 16 1.2 12.6 0.9 10.8 ns 7.7 Switching Characteristics: VCCA = 2.5 V ±0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH tPZL tPZH tPZL FROM (INPUT) TO (OUTPUT) A VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX B 1.6 21.4 1.2 9 0.8 6.2 0.6 4.8 ns B A 1.2 9.3 1 9.1 1 8.9 0.9 8.8 ns OE A 1.4 9 1.4 9 1.4 9 1.4 9 ns OE B 2.3 29.6 1.8 11 1.7 9.3 0.9 6.9 ns OE A 1 10.9 1 10.9 1 10.9 1 10.9 ns OE B 1.7 28.2 1.6 12.9 1.2 9.4 1 6.9 ns Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 9 SN74LVC16T245 SCES636B – AUGUST 2005 – REVISED APRIL 2015 www.ti.com 7.8 Switching Characteristics: VCCA = 3.3 V ±0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH tPZL tPZH tPZL FROM (INPUT) TO (OUTPUT) A VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX B 1.5 21.2 1.1 8.8 0.8 6.1 0.5 4.4 ns B A 0.9 7.2 0.8 6.2 0.7 6.1 0.6 6 ns OE A 1.6 8.2 1.6 8.2 1.6 6.2 1.6 8.2 ns OE B 2.1 29 1.7 10.3 1.5 8.6 0.8 6.3 ns OE A 0.8 7.8 0.8 7.8 0.8 7.8 0.8 7.8 ns OE B 1.6 27.7 1.4 12.4 1.1 8.5 0.9 8.4 ns 7.9 Switching Characteristics: VCCA = 5 V ±0.5 V over recommended operating free-air temperature range, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH tPZL tPZH tPZL VCC = 1.8 V ±0.15 V FROM (INPUT) TO (OUTPUT) A B 1.6 B A OE MIN MAX VCC = 2.5 V ±0.2 V VCC = 3.3 V ±0.3 V VCC = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX 21.4 1 8.8 0.7 6 0.4 4.2 ns 0.7 6.8 0.4 4.8 0.3 4.5 0.3 4.3 ns A 0.3 5.4 0.3 5.4 0.3 5.4 0.3 6.4 ns OE B 2 28.7 1.6 9.7 1.4 8 0.7 5.7 ns OE A 0.7 5.5 0.7 5.5 0.7 5.5 0.7 5.5 ns OE B 1.6 27.6 1.3 11.4 1 8.1 0.9 6 ns 7.10 Operating Characteristics TA = 25°C PARAMETER CpdA CpdB (1) 10 (1) A-port input, B-port output B-port input, A-port output (1) TEST CONDITIONS A-port input, B-port output B-port input, A-port output CL = 0, f = 10 MHz, tr = tf = 1 ns VCCA = VCCB = 1.8 V VCCA = VCCB = 2.5 V VCCA = VCCB = 3.3 V VCCA = VCCB = 5 V UNIT TYP TYP TYP TYP 2 2 2 3 18 19 19 22 18 19 20 22 2 2 2 2 pF Power dissipation capacitance per transceiver. Refer to the TI application report, CMOS Power Consumption and Cpd Calculation, SCAA035 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 SN74LVC16T245 www.ti.com SCES636B – AUGUST 2005 – REVISED APRIL 2015 1.4 5.6 1.2 5.4 1.0 5.2 VOH Voltage (V) VOL Voltage (V) 7.11 Typical Characteristics 0.8 0.6 0.4 4.8 4.6 o -40 C o 25 C 0.2 5.0 o -40 C o 25 C 4.4 o o 85 C 85 C 4.2 0 0 20 40 60 80 100 0 -20 -40 -60 -80 IOL Current (mA) IOH Current (mA) Figure 1. VOL Voltage vs IOL Current Figure 2. VOH Voltage vs IOH Current -100 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 11 SN74LVC16T245 SCES636B – AUGUST 2005 – REVISED APRIL 2015 www.ti.com 8 Parameter Measurement Information 2 Ψ VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 Ψ VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V 15 pF 15 pF 15 pF 15 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 0.15 V 0.15 V 0.3 V 0.3 V VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCA Output Control (low-level enabling) VCCA/2 VCCA/2 0V tPLZ tPZL VCCI Input VCCI/2 VCCI/2 0V tPLH Output tPHL VOH VCCO/2 VOL VCCO/2 VCCO Output Waveform 1 S1 at 2 Ψ VCCO (see Note B) VCCO/2 VOL + VTP VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCCO/2 VOH − VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLH and tPHL are the same as tpd. F. VCCI is the VCC associated with the input port. G. VCCO is the VCC associated with the output port. H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms 12 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 SN74LVC16T245 www.ti.com SCES636B – AUGUST 2005 – REVISED APRIL 2015 9 Detailed Description 9.1 Overview The SN74LVC16T245 is a 16-bit, dual-supply noninverting bidirectional voltage level translation. Pins A and control pins (DIR and OE) are supported by VCCA and pins B are supported by VCCB. The A port is able to accept I/O voltages ranging from 1.65 V to 5.5 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. A high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to low. When OE is set to high, both A and B are in the high-impedance state. This device is fully specified for partial-power-down applications using off output current (Ioff). The VCC isolation feature ensures that if either VCC input is at GND, both ports are put in a high-impedance state. 9.2 Functional Block Diagram 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 2OE 36 13 1B1 2B1 To Seven Other Channels To Seven Other Channels 9.3 Feature Description 9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range Both VCCA and VCCB can be supplied at any voltage from 1.65 V to 5.5 V making the device suitable for translating between any of the low voltage nodes (1.8-V, 2.5-V, and 3.3-V). 9.3.2 Support High-Speed Translation SN74LVC16T245 can support high data rate application. Data rates can be calculated form the maximum propagation delay. This is also dependant on the output load. For example, for a 3.3-V to 5-V conversion, the maximum frequency is 200 MHz. 9.3.3 Partial-Power-Down Mode Operation This device is fully specified for partial-power-down applications using off output current (Ioff). Ioff will prevent backflow current by disabling I/O output circuits when device is in partial power-down mode. 9.3.4 VCC Isolation The VCC isolation feature ensures that if either VCCA or VCCB are at GND, both ports will be in a high-impedance state (IOZ shown in Electrical Characteristics). This prevents false logic levels from being presented to either bus. 9.4 Device Functional Modes The functional modes for the SN74LVC16T245 device are shown in Table 1. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 13 SN74LVC16T245 SCES636B – AUGUST 2005 – REVISED APRIL 2015 www.ti.com Table 1. Function Table (1) (Each Transceiver) CONTROL INPUTS OE (1) 14 OUTPUT CIRCUITS B PORT OPERATION DIR A PORT L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B bus H X Hi-Z Hi-Z Isolation Input circuits of the data I/Os always are active. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 SN74LVC16T245 www.ti.com SCES636B – AUGUST 2005 – REVISED APRIL 2015 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The SN74LVC16T245 device can be used in level-shifting applications for interfacing devices and addressing mixed voltage incompatibility. The SN74LVC16T245 device is ideal for data transmission where direction is different for each channel. 10.1.1 Enable Times Calculate the enable times for the SN74LV16T245 using the following formulas: tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) tPZH (DIR to B) =tPLZ (DIR to A) + tPLH (A to B) tPZL (DIR to B) = tPHZ(DIR to A) + tPHL (A to B) (1) (2) (3) (4) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74LVC16T245 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 15 SN74LVC16T245 SCES636B – AUGUST 2005 – REVISED APRIL 2015 www.ti.com 10.2 Typical Application 1.8 V 3.3 V 0.1 µF 0.1 µF VCCA 1 µF VCCB 1DIR/2DIR 1OE/2OE 1.8-V Controller 3.3-V System SN74LVC16T245 Data 1A1/2A1 1B1/2B1 1A2/2A2 1B2/2B2 1A3/2A3 1B3/2B3 1A4/2A4 1B4/2B4 1A5/2A5 1B5/2B5 1A6/2A6 1B6/2B6 1A7/2A7 1B7/2B7 1A8/2A8 1B8/2B8 GND Data GND GND Figure 4. Typical Application Schematic 10.2.1 Design Requirements This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the intended flow of data and take care not to violate any of the high or low logic levels. It is important that unused data inputs not be floating, as this can cause excessive internal leakage on the input CMOS structure. Make sure to tie any unused input and output ports directly to ground. For this design example, use the parameters listed in Table 2. Table 2. Design Parameters 16 DESIGN PARAMETERS EXAMPLE VALUE Input voltage range 1.65 V to 5.5 V Output voltage 1.65 V to 5.5 V Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 SN74LVC16T245 www.ti.com SCES636B – AUGUST 2005 – REVISED APRIL 2015 10.2.2 Detailed Design Procedure To begin the design process, determine the following: • Input voltage range – Use the supply voltage of the device that is driving the SN74LVC16T245 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port. • Output voltage range – Use the supply voltage of the device that the SN74LVC16T245 device is driving to determine the output voltage range. 10.2.3 Application Curve Voltage (V) Output (5 V) Input (1.8 V) Time (200 ns/div) Figure 5. Translation Up (1.8 V to 5 V) at 2.5 MHz Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 17 SN74LVC16T245 SCES636B – AUGUST 2005 – REVISED APRIL 2015 www.ti.com 11 Power Supply Recommendations The SN74LVC16T245 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts any supply voltage from 1.65 V to 5.5 V and VCCB accepts any supply voltage from 1.65 V to 5.5 V. The A port and B port are designed to track VCCA and VCCB, respectively, allowing for low-voltage bidirectional translation between any of the 1.8-V, 2.5-V and 3.3-V voltage nodes. The output-enable OE input circuit is supplied by VCCA and when the OE input is high, all outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to VCCA through a pullup resistor and must not be enabled until VCCA and VCCB are fully ramped and stable. The minimum value of the pullup resistor to VCCA is determined by the current-sinking capability of the driver. 12 Layout 12.1 Layout Guidelines To • • • 18 ensure reliability of the device, following common printed-circuit-board layout guidelines is recommended. Bypass capacitors should be used on power supplies. Short trace lengths should be used to avoid excessive loading. Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of signals depending on the system requirements. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 SN74LVC16T245 www.ti.com SCES636B – AUGUST 2005 – REVISED APRIL 2015 12.2 Layout Example LEGEND VIA to Power Plane Polygonal Copper Pour VIA to GND Plane (Inner Layer) Keep OE high until VCCA and VCCB are powered up VCCA 1DIR 1OE 48 To System 2 1B1 1A1 47 From Controller To System 3 1B2 1A2 46 From Controller 4 GND GND 45 To System 5 1B3 1A3 44 From Controller To System 6 1B4 1A4 43 From Controller VCCA 42 7 VCCB 8 1B5 1A5 41 From Controller To System 9 1B6 1A6 40 From Controller 10 GND GND 39 11 1B7 1A7 38 From Controller 12 1B8 1A8 37 From Controller To System 13 2B1 2A1 36 From Controller To System 14 2B2 2A2 35 15 GND GND 34 To System 16 2B3 2A3 33 From Controller To System 17 2B4 2A4 32 From Controller 18 VCCB To System SN74AVCH16T245 VCCA VCCA Bypass Capacitor To System To System VCCB VCCA VCCB 1 From Controller VCCA 31 Bypass Capacitor From Controller From Controller 19 2B5 2A5 To System 20 2B6 2A6 29 21 GND GND 28 To System 22 2B7 2A7 27 From Controller To System 23 2B8 2A8 26 From Controller 24 2DIR 2OE 25 VCCA To System VCCA 31 Keep OE high until VCCA and VCCB are powered up Figure 6. SN74LVC16T245 Layout Example Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 19 SN74LVC16T245 SCES636B – AUGUST 2005 – REVISED APRIL 2015 www.ti.com 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation For related documentation see the following: • CMOS Power Consumption and Cpd Calculation, SCAA035 • Implications of Slow or Floating CMOS Inputs, SCBA004 13.2 Trademarks All trademarks are the property of their respective owners. 13.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC16T245 PACKAGE OPTION ADDENDUM www.ti.com 14-Feb-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 74LVC16T245DGGRE4 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC16T245 74LVC16T245DGGRG4 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC16T245 74LVC16T245DGVRG4 ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LDT245 SN74LVC16T245DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC16T245 SN74LVC16T245DGVR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LDT245 SN74LVC16T245DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC16T245 SN74LVC16T245DLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC16T245 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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