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SN74LVC1G00
SCES212AB – APRIL 1999 – REVISED APRIL 2014
SN74LVC1G00 Single 2-Input Positive-NAND Gate
1 Features
•
1
•
•
•
•
•
•
•
•
•
3 Description
2
Available in the Ultra Small 0.64-mm
Package (DPW) With 0.5-mm Pitch
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Provides Down Translation to VCC
Max tpd of 3.8 ns at 3.3 V
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back Drive Protection
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
AV Receiver
Audio Dock: Portable
Blu-ray Player and Home Theater
Embedded PC
MP3 Player/Recorder (Portable Audio)
Personal Digital Assistant (PDA)
Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
Solid State Drive (SSD): Client and Enterprise
TV: LCD/Digital and High-Definition (HDTV)
Tablet: Enterprise
Video Analytics: Server
Wireless Headset, Keyboard, and Mouse
This single 2-input positive-NAND gate is designed
for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G00 performs the Boolean function
Y = A × B or Y = A + B in positive logic.
The CMOS device has high output drive while
maintaining low static power dissipation over a broad
VCC operating range.
The SN74LVC1G00 is available in a variety of
packages, including the ultra-small DPW package
with a body size of 0.8 mm × 0.8 mm.
white space
white space
Device Information(1)
DEVICE NAME
SN74LVC1G00
PACKAGE
BODY SIZE
SOT-23 (5)
2.9mm × 1.6mm
SC70 (5)
2.0mm × 1.25mm
X2SON (4)
0.8mm × 0.8mm
SON (6)
1.45mm × 1.0mm
DSBGA (5)
1.41mm × 0.91mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G00
SCES212AB – APRIL 1999 – REVISED APRIL 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
3
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
3
3
4
4
5
5
5
5
6
6
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, CL = 15 pF ......................
Switching Characteristics, –40°C to 85°C.................
Switching Characteristics, –40°C to 125°C...............
Operating Characteristics..........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 7
9
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
12.2 Layout Example .................................................... 11
13 Device and Documentation Support ................. 12
13.1 Trademarks ........................................................... 12
13.2 Electrostatic Discharge Caution ............................ 12
13.3 Glossary ................................................................ 12
14 Mechanical, Packaging, and Orderable
Information ........................................................... 12
5 Revision History
Changes from Revision AA (March 2014) to Revision AB
Page
•
Added Pin Functions table. .................................................................................................................................................... 3
•
Updated Handling Ratings table. ........................................................................................................................................... 3
•
Added Thermal Information table. ......................................................................................................................................... 4
•
Added Typical Characteristics. .............................................................................................................................................. 6
•
Added Detailed Description section. ...................................................................................................................................... 9
•
Added Application and Implementation section. ................................................................................................................. 10
•
Added Power Supply Recommendations section. .............................................................................................................. 11
•
Added Layout section. ......................................................................................................................................................... 11
Changes from Revision Z (November 2014) to Revision AA
Page
•
Added Applications section. ................................................................................................................................................... 1
•
Added Device Information table. ............................................................................................................................................ 1
•
Added Tstg to Handling Ratings table. .................................................................................................................................... 3
Changes from Revision Y (September 2013) to Revision Z
•
Changed document Features. ................................................................................................................................................ 1
Changes from Revision X (November 2012) to Revision Y
•
2
Page
Page
Extended operating temperature from 85°C to 125°C. .......................................................................................................... 4
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SCES212AB – APRIL 1999 – REVISED APRIL 2014
6 Pin Configuration and Functions
A
1
B
2
GND
3
A
VCC
5
DRL PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
1
B
2
GND
3
VCC
5
A
1
B
2
GND
3
5
4
VCC
Y
A
1
6
B
2
5
GND
3
VCC
A
1
6
VCC
NC
B
GND
2
5
3
4
NC
Y
Y
4
Y
4
DPW PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
Y
4
DSF PACKAGE
(TOP VIEW)
DRY PACKAGE
(TOP VIEW)
GND
NC – No internal connection
See mechanical drawings for dimensions.
3 4
B
2
A
1 5
Y
GND
B
A
1
5
3
4
2
VCC
Y
VCC
Pin Functions
PIN
DESCRIPTION
NAME
DBV, DCK,
DRL, YZP
DRY, DSF
DPW
A
1
1
2
Input
B
2
2
1
Input
GND
3
3
3
Ground
Y
4
4
4
Output
VCC
5
6
5
Power pin
NC
5
Not connected
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
(1)
(2)
(3)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 Handling Ratings
MIN
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MAX
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
UNIT
°C
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions (1)
VCC
Operating
Supply voltage
MAX
5.5
Data retention only
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
UNIT
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
1.65
1.7
VCC = 3 V to 3.6 V
V
2
VCC = 4.5 V to 5.5 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VIL
Low-level input voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 4.5 V to 5.5 V
0.3 × VCC
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current
–8
–16
VCC = 3 V
Low-level output current
Δt/Δv
–32
VCC = 1.65 V
4
VCC = 2.3 V
8
16
VCC = 3 V
Input transition rise or fall rate
(1)
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
mA
–24
VCC = 4.5 V
IOL
V
ns/V
5
Operating free-air temperature
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
SN74LVC1G00
THERMAL METRIC (1)
DBV
DCK
DRL
DRY
YZP
DPW
5 PINS
5 PINS
5 PINS
6 PINS
5 PINS
4 PINS
RθJA
Junction-to-ambient thermal resistance
229
278
243
439
130
340
RθJC(top)
Junction-to-case (top) thermal resistance
164
93
78
277
54
215
RθJB
Junction-to-board thermal resistance
62
65
78
271
51
294
ψJT
Junction-to-top characterization parameter
44
2
10
84
1
41
ψJB
Junction-to-board characterization parameter
62
64
77
271
50
294
RθJC(bot)
Junction-to-case (bottom) thermal resistance
–
–
–
–
–
250
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SCES212AB – APRIL 1999 – REVISED APRIL 2014
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TYP (1)
MIN
IOH = –100 μA
VOH
1.65 V to 5.5 V
VCC – 0.1
VCC – 0.1
1.2
1.2
IOH = –8 mA
2.3 V
1.9
1.9
2.4
2.4
2.3
2.3
3V
IOL = 100 μA
1.65 V to 5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
3.8
0.4
0.4
0.55
0.55
0.55
0.55
0 to 5.5 V
±5
±5
μA
3V
IOL = 32 mA
4.5 V
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
(1)
V
4.5 V
IOL = 16 mA
3.8
UNIT
MAX
IOH = –32 mA
IOL = 24 mA
II
TYP (1)
MIN
1.65 V
IOH = –24 mA
A or B
inputs
MAX
IOH = –4 mA
IOH = –16 mA
VOL
RECOMMENDED
–40°C to 125°C
–40°C to 85°C
IO = 0
V
0
±10
±10
μA
1.65 V to 5.5 V
10
10
μA
3 V to 5.5 V
500
500
μA
3.3 V
4
4
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
7.6 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.2
7.2
0.9
4.4
0.8
3.8
0.8
3.4
ns
7.7 Switching Characteristics, –40°C to 85°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
–40°C to 85°C
PARAMETER
tpd
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.1
9
1.3
5.5
1
4.7
1
4
ns
7.8 Switching Characteristics, –40°C to 125°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
RECOMMENDED
–40°C to 125°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
tpd
A or B
Y
3.1
tpd
A
Y
2
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MAX
MIN
MAX
MIN
MAX
MIN
MAX
9.7
1.3
5.8
1
5
1
4.3
ns
6.4
1
4.2
0.7
3.3
0.7
3.1
ns
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UNIT
5
SN74LVC1G00
SCES212AB – APRIL 1999 – REVISED APRIL 2014
www.ti.com
7.9 Operating Characteristics
TA = 25°C
Cpd
PARAMETER
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
Power dissipation capacitance
f = 10 MHz
22
22
23
25
UNIT
pF
7.10 Typical Characteristics
8
6
TPD
7
5
6
TPD - ns
TPD - ns
4
3
5
4
3
2
2
1
1
TPD
0
-100
0
-50
0
50
Temperature - °C
100
150
0
1
D001
Figure 1. TPD Across Temperature at 3.3V Vcc
6
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2
3
Vcc - V
4
5
6
D002
Figure 2. TPD Across Vcc at 25°C
Copyright © 1999–2014, Texas Instruments Incorporated
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SCES212AB – APRIL 1999 – REVISED APRIL 2014
8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
The SN74LVC1G00 device contains one 2-input positive-NAND gate and performs the Boolean function
Y = A × B or Y = A + B. This device is fully specified for partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down.
The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves
significant board space over other package options while still retaining the traditional manufacturing friendly lead
pitch of 0.5 mm.
9.2 Functional Block Diagram
9.3 Feature Description
•
•
•
•
Wide operating voltage range.
– Operates from 1.65 V to 5.5 V.
Allows down voltage translation.
Inputs accept voltages to 5.5 V.
Ioff feature allows voltages on the inputs and outputs, when VCC is 0 V.
9.4 Device Functional Modes
Function Table
INPUTS
OUTPUT
Y
A
B
H
H
L
L
X
H
X
L
H
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10 Application and Implementation
10.1 Application Information
The SN74LVC1G00 is a high drive CMOS device that can be used for implementing NAND logic with a high
output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V making it Ideal for
driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5 V tolerant
allowing it to translate down to VCC.
10.2 Typical Application
Basic LED Driver
NAND Logic Function
uC or Logic
uC or Logic
uC or Logic
LVC1G00
LVC1G00
uC or Logic
uC or Logic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed total current (continuous
current through VCC or GND) for the part. These limits are located in the Absolute Maximum Ratings
table.
– Outputs should not be pulled above VCC.
10
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Product Folder Links: SN74LVC1G00
SN74LVC1G00
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SCES212AB – APRIL 1999 – REVISED APRIL 2014
Typical Application (continued)
10.2.3 Application Curves
10
8
Icc
Icc
Icc
Icc
1.8V
2.5V
3.3V
5V
Icc - mA
6
4
2
0
-2
-20
0
20
40
Frequency - MHz
60
80
D003
Figure 5. Icc vs Frequency
11 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each Vcc pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply a 0.1-μF capacitor is recommended and if there are multiple Vcc pins then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to Gnd or Vcc whichever make more sense or is more
convenient.
12.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
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Product Folder Links: SN74LVC1G00
11
SN74LVC1G00
SCES212AB – APRIL 1999 – REVISED APRIL 2014
www.ti.com
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC1G00DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C005, C00F, C00J,
C00K, C00R)
(C00H, C00P, C00S)
SN74LVC1G00DBVRE4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C00F
Samples
SN74LVC1G00DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C00F
Samples
SN74LVC1G00DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C005, C00F, C00J,
C00K, C00R)
(C00H, C00P, C00S)
SN74LVC1G00DBVTE4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C00F
Samples
SN74LVC1G00DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C00F
Samples
SN74LVC1G00DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CA5, CAF, CAJ, CA
K, CAR)
(CAH, CAP, CAS)
SN74LVC1G00DCKRE4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CA5
CAS
Samples
SN74LVC1G00DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CA5
CAS
Samples
SN74LVC1G00DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CA5, CAF, CAJ, CA
K, CAR)
(CAH, CAP, CAS)
SN74LVC1G00DCKTG4
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CA5
CAS
Samples
SN74LVC1G00DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
H4
Samples
SN74LVC1G00DRLR
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(CA7, CAR)
Samples
SN74LVC1G00DRY2
ACTIVE
SON
DRY
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CA
Samples
SN74LVC1G00DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CA
Samples
Addendum-Page 1
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC1G00DSF2
ACTIVE
SON
DSF
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CA
Samples
SN74LVC1G00DSFR
ACTIVE
SON
DSF
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CA
Samples
SN74LVC1G00YZPR
ACTIVE
DSBGA
YZP
5
3000
RoHS & Green
Level-1-260C-UNLIM
-40 to 85
(CA7, CAN)
Samples
SNAGCU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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