SN74LVC1G14DBVRG4

Order Now Product Folder Technical Documents Support & Community Tools & Software SN74LVC1G14 SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 SN74LVC1G14 Single Schmitt-Trigger Inverter 1 Features 3 Description • This single Schmitt-trigger inverter is designed for 1.65-V to 5.5-V VCC operation. 1 • • • • • • • • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.6 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation 2 Applications • • • • • • • • • • • • AV Receiver Audio Dock: Portable Blu-ray Player and Home Theater Embedded PC MP3 Player/Recorder (Portable Audio) Personal Digital Assistant (PDA) Power: Telecom/Server AC/DC Supply: Single Controller: Analog and Digital Solid State Drive (SSD): Client and Enterprise TV: LCD/Digital and High-Definition (HDTV) Tablet: Enterprise Video Analytics: Server Wireless Headset, Keyboard, and Mouse The SN74LVC1G14 device contains one inverter and performs the Boolean function Y = A. The device functions as an independent inverter with Schmitttrigger inputs, so the device has different input threshold levels for positive-going (VT+) and negativegoing (VT–) signals to provide hysteresis (ΔVT) which makes the device tolerant to slow or noisy input signals. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. Device Information ORDER NUMBER PACKAGE BODY SIZE (NOM) SN74LVC1G14DBV SOT-23 (5) 2.90 mm × 1.60 mm SN74LVC1G14DCK SC70 (5) 2.00 mm × 1.25 mm SN74LVC1G14DRL SOT-5X3 (5) 1.60 mm × 1.20 mm SN74LVC1G14DRY SON (6) 1.45 mm × 1.00 mm SN74LVC1G14DSF SON (6) 1.00 mm × 1.00 mm SN74LVC1G14YZP DSBGA (5) 1.39 mm × 0.89 mm SN74LVC1G14YZV DSBGA (4) 0.89 mm × 0.89 mm SN74LVC1G14DPW X2SON (5) 0.80 mm x 0.80 mm Logic Diagram (Positive Logic) (DBV, DCK, DRL, DRY, DPW, and YZP Package) A 2 4 Y Logic Diagram (Positive Logic) (YZV Package) A 1 3 Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC1G14 SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 4 4 5 5 6 7 7 7 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics: –40°C to 85°C ................ Switching Characteristics: –40°C to 125°C............... Operating Characteristics.......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 8 Detailed Description .............................................. 9 8.1 Overview ................................................................... 9 8.2 Functional Block Diagrams ....................................... 9 8.3 Feature Description................................................... 9 8.4 Device Functional Modes........................................ 10 9 Application and Implementation ........................ 11 9.1 Application Information............................................ 11 9.2 Typical Application ................................................. 11 10 Power Supply Recommendations ..................... 12 11 Layout................................................................... 12 11.1 Layout Guidelines ................................................. 12 11.2 Layout Example .................................................... 13 12 Device and Documentation Support ................. 14 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 14 14 14 14 14 14 13 Mechanical, Packaging, and Orderable Information ........................................................... 14 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision X (August 2017) to Revision Y Page • Changed New package pinout added to Pin Functions table. Multiple Pin Functions tables condensed to one. ................. 4 • Changed Tj and Tstg lines switched for consistency with other devices. ................................................................................ 4 • Added differentiated ROC temperatures for DPW, YZP and YZV packages ........................................................................ 5 • Changed format of Switching Characteristics tables to include columns for different CL conditions .................................... 7 • Added temperature range to Conditions statement for Switching Characteristics tables ..................................................... 7 • Replaced PMI section with updated load circuit and relevant waveform figures. Collapsed parameter measurement values into one table............................................................................................................................................................... 8 Changes from Revision W (March 2014) to Revision X Page • Added Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, and Layout section ...................................................... 1 • Added DSF, YZP, YZV, and DPW packages to Device Information table............................................................................. 1 • Changed Terminal Configuration and Functions to Pin Configuration and Functions ........................................................... 3 • Moved Storage temperature, Tstg to Absolute Maximum Ratings table. ................................................................................ 4 • Changed Handling Ratings table to ESD Ratings .................................................................................................................. 4 • Changed values in the Thermal Information table to align with JEDEC standards. .............................................................. 5 • Added typical application...................................................................................................................................................... 11 • Added Documentation Support, Receiving Notification of Documentation Updates, and Community Resources .............. 14 Changes from Revision V (Novmber 2012) to Revision W Page • Added DPW Package ............................................................................................................................................................. 1 • Added Applications ................................................................................................................................................................. 1 • Moved Tstg to Handling Ratings table ..................................................................................................................................... 4 2 Submit Documentation Feedback Copyright © 1999–2018, Texas Instruments Incorporated Product Folder Links: SN74LVC1G14 SN74LVC1G14 www.ti.com SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View N.C. 1 A 2 GND DCK Package 5-Pin SC70 Top View VCC 5 3 N.C. 1 A 2 GND 3 DRL Package 5-Pin SOT-5X3 Top View 1 A 2 GND 3 5 4 NC VCC Y N.C. 1 6 A 2 5 N.C. GND 3 4 Y VCC Y DSF Package 6-Pin SON Top View VCC Y A 4 DRY Package 6-Pin SON Top View DPW Package 5-Pin X2SON Top View GND VCC Y 4 N.C. 5 N.C. 1 6 VCC A 2 5 N.C. GND 3 4 Y See mechanical drawings for dimensions. N.C. – No internal connection YZP Package 5-Pin DSBGA Bottom View 1 C GND B A YZV Package 4-Pin DSBGA Bottom View 2 Y 1 2 B GND Y A A VCC A DNU VCC Not to scale Not to scale DNU – Do not use Submit Documentation Feedback Copyright © 1999–2018, Texas Instruments Incorporated Product Folder Links: SN74LVC1G14 3 SN74LVC1G14 SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 www.ti.com Pin Functions PIN DBV, DCK, DRL, DPW DRY, DSF A 2 GND 3 N.C. NAME I/O DESCRIPTION YZP YZV 2 B1 A1 I 3 C1 B1 — Ground 1 1, 5 — — — No internal connection (1) DNU — — A1 — — Do not use (2) VCC 5 6 A2 A2 — Positive Supply Y 4 4 C2 B2 O Signal Output (1) (2) Signal Input Pins labeled N.C. can be connected to any signal or voltage source, including ground. They should always be soldered to the board. Pins labeled DNU should not be connected to any signal or voltage source, including ground. They should always be soldered to the board. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage (2) MIN MAX UNIT –0.5 6.5 V VI Input voltage –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCC or GND ±100 mA 150 °C 150 °C Tj Maximum junction temperature Tstg Storage temperature (1) (2) (3) (3) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. 6.2 ESD Ratings VALUE V(ESD) (1) (2) 4 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 1000 Machine Model (A115-A) 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 1999–2018, Texas Instruments Incorporated Product Folder Links: SN74LVC1G14 SN74LVC1G14 www.ti.com SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN MAX Operating 1.65 5.5 Data retention only 1.5 UNIT VCC Supply voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 1.65 V –4 VCC = 2.3 V IOH High-level output current –8 –16 VCC = 3 V Low-level output current –32 VCC = 1.65 V 4 8 16 VCC = 3 V (1) Operating free-air temperature mA 24 VCC = 4.5 V TA mA –24 VCC = 4.5 V VCC = 2.3 V IOL V 32 YZP, YZV, and DPW packages –40 85 All other packages –40 125 °C All unused inputs of the device must be held at VCC or GND to assure proper device operation. See Implications of Slow or Floating CMOS Inputs. 6.4 Thermal Information SN74LVC1G14 THERMAL METRIC (1) DBV (SOT-23) DCK (SC70) DRL (SOT-5X3) DRY (SON) DPW (X2SON) YZV (DSBGA) YZP (DSBGA) 5 PINS 5 PINS 5 PINS 5 PINS 5 PINS 4 PINS 5 PINS UNIT RθJA Junction-to-ambient thermal resistance 247.2 276.1 296.2 369.6 522.9 168.2 146.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 154.5 178.9 137.3 257.6 250.5 2.1 1.4 °C/W RθJB Junction-to-board thermal resistance 86.8 70.9 145.3 230.8 384.0 55.9 39.8 °C/W ψJT Junction-to-top characterization parameter 58.0 47.0 14.7 77.2 46.5 1.1 0.7 °C/W ψJB Junction-to-board characterization parameter 86.4 69.3 145.9 231.0 382.8 56.3 39.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A 174.1 N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 1999–2018, Texas Instruments Incorporated Product Folder Links: SN74LVC1G14 5 SN74LVC1G14 SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 www.ti.com 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAME TER TEST CONDITIONS VCC –40°C to 125°C (1) –40°C to 85°C MIN TYP (2) MAX MIN TYP MAX VT+ Positivegoing input threshold voltage 1.65 V 0.79 1.16 .79 1.16 2.3 V 1.11 1.56 1.11 1.56 3V 1.5 1.87 1.5 1.87 4.5 V 2.16 2.74 2.16 2.74 5.5 V 2.61 3.33 2.61 3.33 VT– Negativegoing input threshold voltage 1.65 V 0.39 0.62 .39 .64 2.3 V 0.58 0.87 .58 .89 3V 0.84 1.14 .84 1.16 4.5 V 1.41 1.79 1.41 1.79 1.87 2.29 VT– Negativegoing input threshold voltage DBV, DCK, DRL, DRY, DSF, YZV and YZP packages DPW package ΔVT Hysteresis (VT+ – VT–) 5.5 V 1.87 2.29 1.65 V 0.44 0.67 2.3 V 0.63 0.92 3V 0.89 1.19 4.5 V 1.46 1.84 5.5 V 1.92 2.34 1.65 V 0.37 0.62 0.37 0.62 2.3 V 0.48 0.77 0.48 0.77 3V 0.56 0.87 0.56 0.87 4.5 V 0.71 1.04 0.71 1.04 0.71 1.11 0.71 1.11 5.5 V 1.65 V to 4.5 V IOL = –100 µA VOH VOL 1.2 IOL = –8 mA 2.3 V 1.9 1.9 2.4 2.4 2.3 2.3 3.8 3.8 3V 4.5 V IOL = 100 µA 1.65 V to 4.5 V 0.1 0.1 IOL = 4 mA 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 0.4 0.4 0.55 0.55 3V V IOL = 32 mA 4.5 V 0.55 0.7 0 to 5.5 V ±5 ±5 µA 0 ±10 ±10 µA 1.65 V to 5.5 V 10 10 µA 3 V to 5.5 V 500 500 µA VI or VO = 5.5 V ICC VI = 5.5 V or GND, IO = 0 ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND 6 V A VI = 5.5 V or GND input Ioff (2) V V IOL = –32 mA IOL = 24 mA (1) VCC – 0.1 1.2 IOL = 16 mA II VCC – 0.1 1.65 V IOL = –24 mA V V IOL = –4 mA IOL = –16 mA UNIT 3.3 V 4.5 4.5 pF These specifications do not apply to DPW, YZV and YZP packages. DPW, YZV and YZP have a recommended operating free-air temperature range of –40°C to 85°C. All typical values are at VCC = 3.3 V, TA = 25°C. Submit Documentation Feedback Copyright © 1999–2018, Texas Instruments Incorporated Product Folder Links: SN74LVC1G14 SN74LVC1G14 www.ti.com SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 6.6 Switching Characteristics: –40°C to 85°C over recommended operating free-air temperature range, (–40°C to 85°C unless otherwise noted) (see ) FROM (INPUT) PARAMETER tpd TO (OUTPUT) A Y CL = 30 pF or 50 pF CL = 15 pF VCC MIN MAX MIN 1.8 V ± 0.15 V 2.8 9.9 3.8 11 2.5 V ± 0.2 V 1.6 5.5 2 6.5 3.3 V ± 0.3 V 1.5 4.6 1.8 5.5 5 V ± 0.5 V 0.9 4.4 1.2 5 UNIT MAX ns 6.7 Switching Characteristics: –40°C to 125°C over operating free-air temperature range, (–40°C to 125°C unless otherwise noted) FROM (INPUT) PARAMETER tpd TO (OUTPUT) A CL = 30 pF or 50 pF VCC Y MIN MAX 1.8 V ± 0.15 V 3.8 13 2.5 V ± 0.2 V 2 8 3.3 V ± 0.3 V 1.8 6.5 5 V ± 0.5 V 1.2 6 UNIT ns 6.8 Operating Characteristics TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance f = 10 MHz VCC TYP 1.8 V 20 2.5 V 21 3.3 V 22 5V 25 UNIT pF 6.9 Typical Characteristics TA = 25°C 5.5 0.35 5 0.3 4.5 0.25 VOL (V) VOH (V) 4 3.5 0.2 0.15 3 0.1 2.5 VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V 2 VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V 0.05 0 1.5 0 5 10 15 20 IOH (mA) 25 30 35 0 Figure 1. Typical VOH vs IOH - 25°C 5 10 15 20 IOL (mA) 25 30 Figure 2. Typical VOL vs IOL - 25°C Submit Documentation Feedback Copyright © 1999–2018, Texas Instruments Incorporated Product Folder Links: SN74LVC1G14 35 7 SN74LVC1G14 SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 www.ti.com 7 Parameter Measurement Information • • Input pulse is supplied by generator having the following characteristics: PRR ≤ 10MHz. ZO = 50Ω. The outputs are measured one at a time, with one transition per measurement. From Output Under Test (1) CL(1) RL CL includes probe and jig capacitance. Figure 3. Load Circuit Table 1. Parameter Measurement Conditions Vcc INPUTS VM VLOAD ≤ 2 ns Vcc/2 2 × Vcc Vcc ≤ 2 ns Vcc/2 2 × Vcc 3.3 V ± 0.3 V 3V ≤ 2.5 ns 1.5 V 6V 5 V ± 0.5 V Vcc ≤ 2.5 ns Vcc/2 2 × Vcc VI tr/tf 1.8 V ± 0.15 V Vcc 2.5 V ± 0.2 V CL RL 15 pF 1 MΩ 30 pF 1 kΩ 15 pF 1 MΩ 30 pF 500 Ω 15 pF 1 MΩ 50 pF 500 Ω 15 pF 1 MΩ 50 pF 500 Ω VD 0.15 V 0.15 V 0.3 V 0.3 V VI Input VM VM 0V tPLH (1) tPHL (1) VOH Output VM VM VOL tPLH(1) tPHL(1) VOH Output VM VM VOL (1) The maximum value of tpd is the worst case of tPLH or tPHL Figure 4. Voltage Waveforms, Propagation Delay Times, Inverting and Non-Inverting Outputs 8 Submit Documentation Feedback Copyright © 1999–2018, Texas Instruments Incorporated Product Folder Links: SN74LVC1G14 SN74LVC1G14 www.ti.com SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 8 Detailed Description 8.1 Overview The SN74LVC1G14 single Schmitt-trigger inverter is designed for 1.65 V to 5.5 V operation and performs the Boolean function Y = A. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. 8.2 Functional Block Diagrams A 2 4 Y Figure 5. Logic Diagram (Positive Logic) (DBV, DCK, DRL, DRY, DPW, and YZP Package) A 1 3 Y Figure 6. Logic Diagram (Positive Logic) (YZV Package) 8.3 Feature Description 8.3.1 Balanced High-Drive CMOS Push-Pull Outputs A balanced output allows the device to sink and source similar currents. The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings Absolute Maximum Ratings] must be followed at all times. 8.3.2 CMOS Schmitt-Trigger Inputs Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, using ohm's law (R = V ÷ I). The Schmitt-trigger input architecture provides hysteresis as define in the Electrical Characteristics, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly will also increase dynamic current consumption of the device. Submit Documentation Feedback Copyright © 1999–2018, Texas Instruments Incorporated Product Folder Links: SN74LVC1G14 9 SN74LVC1G14 SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 www.ti.com Feature Description (continued) 8.3.3 Clamp Diodes The inputs and outputs to this device have negative clamping diodes. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input negative-voltage and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. Device VCC Logic Input -IIK Output -IOK GND Figure 7. Electrical Placement of Clamping Diodes for Each Input and Output 8.3.4 Partial Power Down (Ioff) The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical Characteristics. 8.3.5 Over-Voltage Tolerant Inputs Input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the Absolute Maximum Ratings. 8.4 Device Functional Modes Table 2 lists the functional modes of the SN74LVC1G14 device. Table 2. Function Table INPUT A 10 OUTPUT Y H L L H Submit Documentation Feedback Copyright © 1999–2018, Texas Instruments Incorporated Product Folder Links: SN74LVC1G14 SN74LVC1G14 www.ti.com SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information Mechanical input elements, such as push buttons or rotary knobs, offer simple ways to interact with electronic systems. Typically, these elements have recoil or bouncing, where the mechanical element makes and breaks contact multiple times during human interaction. This bouncing can cause one or more repeated signals to be passed, triggering multiple actions when only a single input was intended. One potential solution to mitigating these multiple inputs is by utilizing a Schmitt-trigger to create a debounce circuit. Figure 8 shows an example of this solution. 9.2 Typical Application The input due to the push button switches multiple times, causing the output of a non Schmitt-trigger device to trigger multiple times, while the Schmitt-trigger input device with RC delay limits the output pulse to a single pulse desired by the user. The separated positive and negative input voltage threshold values, see Figure 9, prevent multiple triggers from occurring. VCC R1 R2 A Y OUTPUT C1 Figure 8. Push Button Debounce Circuit Schematic 9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions: – For specified high and low levels, see (VT+ and VT-) in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating Conditions table at any valid VCC. 2. Recommended Output Conditions: – Load currents should not exceed (IO max) per output and should not exceed (Continuous current through VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table. Submit Documentation Feedback Copyright © 1999–2018, Texas Instruments Incorporated Product Folder Links: SN74LVC1G14 11 SN74LVC1G14 SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 www.ti.com Typical Application (continued) 9.2.3 Application Curve Figure 9 is created from the values given in the Electrical Characteristics. Linear interpolation shows the values between each given point. 3.5 Input Voltage (V) 3 2.5 VT+(min) VT+(max) VT-(min) VT-(max) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 Supply Voltage (V) 4.5 5 5.5 D001 Figure 9. Interpolated Threshold Voltages vs. VCC 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions table. The VCC pin must have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is recommended, and it is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-µF and 1µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for best results. 11 Layout 11.1 Layout Guidelines Even low data rate digital signals can contain high-frequency signal components due to fast edge rates. When a printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections. An example layout is given in Figure 10 for the DPW (X2SON-5) package. This example layout includes a 0402 (metric) capacitor and uses the measurements found in the example board layout appended to this end of this datasheet. A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be used to trace out the center pin connection through another board layer, or it can be left out of the layout 12 Submit Documentation Feedback Copyright © 1999–2018, Texas Instruments Incorporated Product Folder Links: SN74LVC1G14 SN74LVC1G14 www.ti.com SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 11.2 Layout Example 4 mil 0402 0.1 …F Bypass Capacitor 8 mil 8 mil 8 mil SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK, TYP Figure 10. Example Layout With DPW (X2SON-5) Package Submit Documentation Feedback Copyright © 1999–2018, Texas Instruments Incorporated Product Folder Links: SN74LVC1G14 13 SN74LVC1G14 SCES218Y – APRIL 1999 – REVISED NOVEMBER 2018 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: Implications of Slow or Floating CMOS Inputs 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks NanoFree, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Documentation Feedback Copyright © 1999–2018, Texas Instruments Incorporated Product Folder Links: SN74LVC1G14 PACKAGE OPTION ADDENDUM www.ti.com 8-Jun-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LVC1G14DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C145, C14F, C14J, C14K, C14R) (C14H, C14S) SN74LVC1G14DBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C14F Samples SN74LVC1G14DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C14F Samples SN74LVC1G14DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C145, C14F, C14J, C14K, C14R) (C14H, C14S) SN74LVC1G14DBVTE4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C14F Samples SN74LVC1G14DBVTG4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C14F Samples SN74LVC1G14DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CF5, CFF, CFJ, CF K, CFR, CFT) (CFH, CFS) SN74LVC1G14DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CF5 CFS SN74LVC1G14DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CF5, CFF, CFJ, CF K, CFR, CFT) (CFH, CFS) SN74LVC1G14DCKTE4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CF5 CFS Samples SN74LVC1G14DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CF5 CFS Samples SN74LVC1G14DPWR ACTIVE X2SON DPW 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 9H Samples SN74LVC1G14DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 (CF7, CFR) Samples SN74LVC1G14DRLRG4 ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 (CF7, CFR) Samples SN74LVC1G14DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CF Samples SN74LVC1G14DSFR ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CF Samples Addendum-Page 1 Samples Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 8-Jun-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LVC1G14YZPR ACTIVE DSBGA YZP 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 (CF7, CFN) Samples SN74LVC1G14YZVR ACTIVE DSBGA YZV 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 CF (7, N) Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of