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SN74LVC1G19
SCES464G – JUNE 2003 – REVISED AUGUST 2015
SN74LVC1G19 1-of-2 Decoder and Demultiplexer
1 Features
2 Applications
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Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to VCC
Maximum tpd of 4 ns at 3.3 V
Low Power Consumption, 10-µA Maximum ICC
±24-mA Output Drive at 3.3 V
VOLP (Output Ground Bounce)
2 V Typical at VCC = 3.3 V, TA = 25°C
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
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•
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AV Receivers
Audio Docks: Portable
Blu-ray® Players and Home Theater
MP3 Players/Recorders
Personal Digital Assistants (PDAs)
Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
Solid State Drives (SSDs): Client and Enterprise
TVs: LCD/Digital and High-Definition (HDTVs)
Tablets: Enterprise
Video Analytics: Server
Wireless Headsets, Keyboards, and Mice
3 Description
This decoder/demultiplexer is designed for 1.65-V to
5.5-V VCC operation.
The SN74LVC1G19 device is a 1-of-2 decoder /
demultiplexer. When E input is high, the decoder will
be disabled and both outputs will be high. When E
input is low, the A input selects which output will be
low.
This device is fully specified for partial-power-down
applications using Ioff.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1G19DBV
SOT-23 (6)
2.9 mm × 1.6 mm
SN74LVC1G19DCK
SC70 (6)
2.0 mm × 1.25 mm
SN74LVC1G19DRL
SOT (6)
1.6 mm × 1.2 mm
SN74LVC1G19DRY
SON (6)
1.45 mm × 1.0 mm
SN74LVC1G19YZP
DSBGA (6)
1.41 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Y0
Y1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G19
SCES464G – JUNE 2003 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
5
5
6
6
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, CL = 15 pF ......................
Switching Characteristics, CL = 30 pF or 50 pF........
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (July 2012) to Revision G
Page
•
Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table,
Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Updated Ioff in Features. ......................................................................................................................................................... 1
2
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5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
DCK Package
6-Pin SC70
Top View
A
1
6
Y0
GND
2
5
VCC
E
3
A
1
6
Y0
GND
2
5
VCC
E
3
4
Y1
Y1
4
DRY Package
6-Pin SON
Top View
DRL Package
6-Pin SOT
Top View
A
1
6
Y0
GND
2
5
VCC
E
3
4
Y1
A
1
6
Y0
GND
2
5
VCC
E
3
4
Y1
YZP Package
6-Pin DSBGA
Bottom View
E
3 4
GND
2 5
A
1 6
Y1
VCC
Y0
Pin Functions (1)
PIN
NAME
NO.
I/O
DESCRIPTION
A
1
I
GND
2
—
E
3
I
Enable input, active low
Y1
4
O
Output 1, low when selected by A high and E low
VCC
5
—
Power pin
Y0
6
O
Output 0, low when selected by A low and E low
(1)
Adress input, selects which output goes low.
Ground
See mechanical drawings for dimensions
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
VESD
(1)
(2)
4
Electrostatic
discharge
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged-Device Model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
Machine model
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Operating
Supply voltage
Data retention only
1.65
5.5
1.7
VCC = 3 V to 3.6 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
Low-level input voltage
V
V
2
VCC = 4.5 V to 5.5 V
VIL
UNIT
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
MAX
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
V
0.3 × VCC
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
VCC = 1.65 V
–4
VCC = 2.3 V
–8
–16
VCC = 3 V
VCC = 4.5 V
–32
VCC = 1.65 V
4
VCC = 2.3 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
8
16
VCC = 3 V
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
(1)
mA
–24
ns/V
5
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LVC1G19
THERMAL METRIC (1)
RθJA
(1)
Junction-to-ambient thermal resistance
DBV (SOT23)
DCK (SC70)
DRL (SOT)
DRY (SON)
YZP
(DSBGA)
6 PINS
6 PINS
6 PINS
6 PINS
6 PINS
165
259
142
234
123
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 µA
VOH
1.65 V to 5.5 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.9
VOL
2.3
IOH = –32 mA
4.5 V
IOL = 100 µA
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
IOL = 16 mA
3.8
0.4
3V
IOL = 24 mA
IOL = 32 mA
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
IO = 0
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
CI
VI = VCC or GND
(1)
All typical values are at VCC = 3.3 V, TA = 25°C.
V
0.55
4.5 V
II
UNIT
V
2.4
3V
IOH = –24 mA
MAX
VCC – 0.1
IOH = –4 mA
IOH = –16 mA
TYP (1)
MIN
0.55
0 to 5.5 V
±1
µA
0
±10
µA
1.65 V to 5.5 V
10
µA
3 V to 5.5 V
500
µA
3.3 V
3.5
pF
6.6 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or E
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.5
16.1
1.5
5.9
1
4
0.5
2.8
UNIT
ns
6.7 Switching Characteristics, CL = 30 pF or 50 pF
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or E
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.2
16.1
1.5
6.5
1.1
5.2
0.5
3.9
UNIT
ns
6.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
15.5
16
16
18
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UNIT
pF
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16.00
16.00
12.00
12.00
Max tpd (ns)
Max tpd (ns)
6.9 Typical Characteristics
8.00
4.00
0.00
0.00
4.00
tpd (}u}"}z
CL= 15 pF
1.00
2.00
8.00
3.00
4.00
VCC Supply Voltage (V)
5.00
6.00
tpd (}u}"}z
CL= 30 pF to 50 pF
0.00
0.00
2.00
3.00
4.00
5.00
VCC Supply Voltage (V)
C001
Figure 1. Time Propagation Delay vs VCC, CL= 15 pF
1.00
6.00
C001
Figure 2. Time Propagation Delay vs VCC, CL= 30 pF or
50 pF
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
This decoder/demultiplexer is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G19 device is a 1-of-2 decoder/demultiplexer. This device decodes the 1-bit address on input A
and places a logic low on the matching address output, Y0 or Y1 , when the enable (E) input signal is low.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
8.2 Functional Block Diagram
Y0
Y1
8.3 Feature Description
SN74LVC1G19 is available in NanoFree package. NanoFree is a major breakthrough in IC packaging concepts,
it is a bare die package developed for applications that require the smallest possible package. The device
supports 5-V VCC Operation. All Inputs accept voltages up to 5.5 V. ±24-mA output drive at 3.3 V. The maximum
time propagation delay (tpd ) is 5.4 ns at 3.3 V. Low Power Consumption, 10-μA Max ICC. Typical output ground
bounce (VOLP ) and Output VOH Undershoot (VOHV). This device is fully specified for partial-power-down
applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it
is powered down. The SN74LVC1G19 device has isolation during power off. Ioff supports live insertion, partialpower-down mode and back drive protection.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC1G19.
Table 1. Function Table
INPUTS
E
10
OUTPUTS
A
Y0
Y1
H
L
L
L
L
H
H
L
H
X
H
H
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G19 device is a 1-of-2 decoder/demultiplexer. This device decodes the 1 bit address on input A
and places a logic low on the matching address output, Y0 or Y1 , when the enable (E) input signal is low. It can
produce 24 mA of drive current at 3.3 V making it ideal for driving multiple outputs.
9.2 Typical Application
VCC
0.1 PF
9
1
5
E 3
6
2
4
VCC
PCU
0
Device
Device
Figure 5. Typical Application Diagram
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. Outputs can be combined to produce higher drive but the
high drive will also create faster edges into light loads so routing and load conditions should be considered to
prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see (Δt/ΔV) in Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
– Load currents must not exceed 50 mA per output and 100 mA total for the part.
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
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Typical Application (continued)
9.2.3 Application Curve
10
Icc
Icc
Icc
Icc
9
8
1.8V
2.5V
3.3V
5V
Icc - mA
7
6
5
4
3
2
1
0
0
20
40
Frequency - MHz
60
80
D003
Figure 6. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Absolute Maximum Ratings table.
Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. If there are multiple VCC terminals then 0.01-μF or 0.022-μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor must be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
12
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Copyright © 2003–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G19
SN74LVC1G19
www.ti.com
SCES464G – JUNE 2003 – REVISED AUGUST 2015
12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
Blu-ray is a registered trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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Copyright © 2003–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G19
13
PACKAGE OPTION ADDENDUM
www.ti.com
2-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC1G19DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(C195, C19K, C19R)
Samples
SN74LVC1G19DBVRE4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(C195, C19K, C19R)
Samples
SN74LVC1G19DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(C195, C19K, C19R)
Samples
SN74LVC1G19DCKR
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(CY5, CYF, CYK, CY
R)
Samples
SN74LVC1G19DCKRE4
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CY5
Samples
SN74LVC1G19DCKRG4
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CY5
Samples
SN74LVC1G19DRLR
ACTIVE
SOT-5X3
DRL
6
4000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(1JZ, CY7, CYR)
Samples
SN74LVC1G19DRLRG4
ACTIVE
SOT-5X3
DRL
6
4000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(1JZ, CY7, CYR)
Samples
SN74LVC1G19DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CY
Samples
SN74LVC1G19YZPR
ACTIVE
DSBGA
YZP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(CY7, CYN)
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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