SN74LVC1G74RSER

SN74LVC1G74 SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 SN74LVC1G74 Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset 1 Features 3 Description • This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. • • • • • • • • • • • Available in the Texas Instruments NanoFree™ package Supports 5-V VCC operation Inputs accept voltages to 5.5-V Supports down translation to VCC Maximum tpd of 5.9-ns at 3.3-V Low power consumption, 10-µA maximum ICC ±24-mA output drive at 3.3-V Typical VOLP (output ground bounce) < 0.8-V at VCC = 3.3-V, TA = 25°C Typical VOHV (output VOH undershoot) > 2-V at VCC = 3.3 V, TA = 25°C Ioff supports live insertion, partial-power-down mode, and back-drive protection Latch-up performance exceeds 100 mA per JESD 78, class II ESD protection exceeds JESD 22 – 2000-V human-body model – 200-V machine model – 1000-V charged-device model NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. A low level at the preset ( PRE) or clear ( CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 2 Applications • • • • • • Device Information Servers LED displays Network switch Telecom infrastructure Motor drivers I/O expanders PART NUMBER SN74LVC1G74 (1) PACKAGE (1) BODY SIZE SM8 (8) 2.95 mm × 2.80 mm US8 (8) 2.30 mm × 2.00 mm X2SON (8) 1.40 mm × 1.00 mm UQFN (8) 1.50 mm × 1.50 mm For all available packages, see the orderable addendum at the end of the data sheet. PRE D Q CLK Q CLR Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC1G74 www.ti.com SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................4 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings........................................ 5 6.2 ESD Ratings............................................................... 5 6.3 Recommended Operating Conditions.........................6 6.4 Thermal Information....................................................6 6.5 Electrical Characteristics.............................................7 6.6 Timing Requirements.................................................. 7 6.7 Switching Characteristics............................................7 6.8 Operating Characteristics........................................... 8 6.9 Typical Characteristics................................................ 8 7 Parameter Measurement Information............................ 9 8 Detailed Description......................................................10 8.1 Overview................................................................... 10 8.2 Functional Block Diagram......................................... 10 8.3 Feature Description...................................................10 8.4 Device Functional Modes..........................................10 9 Application and Implementation.................................. 11 9.1 Application Information..............................................11 9.2 Typical Power Button Circuit..................................... 11 10 Power Supply Recommendations..............................12 11 Layout........................................................................... 13 11.1 Layout Guidelines................................................... 13 11.2 Layout Example...................................................... 13 12 Device and Documentation Support..........................14 12.1 Receiving Notification of Documentation Updates..14 12.2 Support Resources................................................. 14 12.3 Trademarks............................................................. 14 12.4 Electrostatic Discharge Caution..............................14 12.5 Glossary..................................................................14 13 Mechanical, Packaging, and Orderable Information.................................................................... 14 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (April 2020) to Revision G (September 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated the Application and Information section............................................................................................. 11 • Updated the Device Power Button Circuit figure Typical Power Button Circuit section.................................... 11 Changes from Revision E (Janurary 2015) to Revision F (April 2020) Page • Match RSE pinout with signal names................................................................................................................. 4 Changes from Revision D (January 2013) to Revision E (Janurary 2015) Page • Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1 • Deleted Ordering Information table.....................................................................................................................1 • Updated Features .............................................................................................................................................. 1 Changes from Revision C (November 2012) to Revision D (January 2013) Page • Deleted Thermal data for DQE Package............................................................................................................ 1 • Added Thermal data for DQE Package.............................................................................................................. 6 Changes from Revision B (March 2012) to Revision C (November 2012) Page • Added preview for RES part............................................................................................................................... 1 • Added QFN package ordering information....................................................................................................... 14 Changes from Revision A (November 2011) to Revision B (February 2012) Page • Added SN74LVC1G74DCURG4 part number to ORDERING INFORMATION table....................................... 14 Changes from Revision * (October 2009) to Revision A (November 2011) Page • Changed Ioff description in Features ..................................................................................................................1 • Changed temperature range for DCT and DCU package from (−40°C to 85°C) to (−40°C to 125°C)............... 6 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 www.ti.com • • SN74LVC1G74 SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 Changed Timing Requirements table................................................................................................................. 7 Changed Switching Requirements table.............................................................................................................7 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 3 SN74LVC1G74 www.ti.com SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 5 Pin Configuration and Functions DCT PACKAGE (TOP VIEW) CLK 1 D 2 DCU PACKAGE (TOP VIEW) 8 VCC 7 PRE Q 3 6 CLR GND 4 5 Q CLK D Q GND 1 8 2 7 3 6 4 5 VCC PRE CLR Q See mechanical drawings for dimensions. Figure 5-1. DCT 8-Pin SM8 and DCU 8-Pin VSSOP Package Top View DQE PACKAGE (TOP VIEW) CLK D Q GND 1 8 2 7 3 6 4 5 VCC PRE CLR Q RSE PACKAGE (TOP VIEW) VCC PRE CLR Q 1 8 7 2 3 6 4 5 CLK D Q GND See mechanical drawings for dimensions Figure 5-2. DQE 8-Pin X2SON and RSE UQFN 8-Pin Package Top View Pin Functions PIN NAME 4 NO. TYPE DESCRIPTION CLK 1 I Clock input CLR 6 I Clear input − Pull low to set Q output low D 2 I Input GND 4 — PRE 7 I Preset input − Pull low to set Q output high Q 5 O Output Q 3 O Inverted output VCC 8 — Supply Ground Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 SN74LVC1G74 www.ti.com SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC MIN MAX Supply voltage range –0.5 6.5 V range(2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 VI Input voltage VO Voltage range applied to any output in the high-impedance or power-off state(2) state(2) (3) UNIT VO Voltage range applied to any output in the high or low IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA 150 °C Continuous current through VCC or GND Tstg (1) (2) (3) Storage temperature range –65 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The value of VCC is provided in the Recommended Operating Conditions table. 6.2 ESD Ratings PARAMETER DEFINITION Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all V(ESD) (1) (2) Electrostatic discharge VALUE UNIT 2000 V pins(1) Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 5 SN74LVC1G74 www.ti.com SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted)(1) VCC Operating Supply voltage Data retention only 1.65 5.5 VCC = 3 V to 3.6 V VI Input voltage VO Output voltage V 2 0.7 × VCC VCC = 1.65 V to 1.95 V Low-level input voltage 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V 0.3 × VCC 5.5 V 0 VCC V –4 VCC = 2.3 V High-level output current –8 –16 VCC = 3 V Low-level output current Δt/Δv Input transition rise or fall rate –32 VCC = 1.65 V 4 VCC = 2.3 V 8 16 VCC = 3 V VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 –40 DQE Package 85 °C DCT Package –40 DCU Package (1) ns/V 5 RSE Package Operating free-air temperature mA 24 VCC = 5 V ± 0.5 V TA mA –24 VCC = 4.5 V IOL V 0 VCC = 1.65 V IOH V 1.7 VCC = 4.5 V to 5.5 V VIL UNIT 0.65 × VCC VCC = 2.3 V to 2.7 V High-level input voltage MAX 1.5 VCC = 1.65 V to 1.95 V VIH MIN 125 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 6.4 Thermal Information SN74LVC1G74 THERMAL RθJA (1) 6 METRIC(1) Junction-to-ambient thermal resistance DCT DCU RSE DQE 8 PINS 8 PINS 8 PINS 8 PINS 220 227 243 261 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 SN74LVC1G74 www.ti.com SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 4.5 V IOL = 100 µA 1.65 V to 5.5 V 0.1 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 VI = 5.5 V or GND VI or VO = 5.5 V ICC VI = 5.5 V or GND, IO = 0 ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND V 0.55 4.5 V Ioff (1) 0.4 3V IOL = 32 mA II 3.8 IOL = 4 mA IOL = 24 mA Data or control inputs 2.3 IOH = –32 mA IOL = 16 mA UNIT V 2.4 3V IOH = –24 mA MAX VCC – 0.1 IOH = –4 mA IOH = –16 mA VOL MIN TYP(1) VCC 0.55 0 to 5.5 V ±5 µA 0 ±10 µA 1.65 V to 5.5 V 10 µA 3 V to 5.5 V 500 µA 3.3 V 5 pF All typical values are at VCC = 3.3 V, TA = 25°C. 6.6 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1) –40°C to 85°C PARAMETE R FROM (INPUT) TO (OUTPUT) VCC = 1.8 V MIN fclock tw tsu MAX VCC = 2.5 V MIN 80 MAX –40°C to 125°C VCC = 3.3 V MIN 175 MAX VCC = 5 V MIN 175 MAX VCC = 3.3 V MIN MAX 200 VCC = 5 V MIN 175 MAX 200 MHz CLK 6.2 2.7 2.7 2 2.7 2 PRE or CLR low 6.2 2.7 2.7 2 2.7 2 Data 2.9 1.7 1.3 1.1 1.3 1.1 PRE or CLR inactive 1.9 1.4 1.2 1 1.2 1.2 0 0.3 1.2 0.5 1.2 0.5 th UNIT ns ns ns 6.7 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1) –40°C to 85°C PARAMETE R FROM (INPUT) TO (OUTPUT) VCC = 1.8 V MIN fmax CLK tpd MAX 80 PRE or CLR low VCC = 2.5 V MIN MAX 175 –40°C to 125°C VCC = 3.3 V MIN MAX 175 VCC = 5 V MIN MAX 200 VCC = 3.3 V MIN MAX 175 VCC = 5 V MIN MAX 200 MHz Q 4.8 13.4 2.2 7.1 2.2 5.9 1.4 4.1 2.2 7.9 1.4 6.1 Q 6 14.4 3 7.7 2.6 6.2 1.6 4.4 2.6 8.2 1.6 6.4 4.4 12.9 2.3 7 1.7 5.9 1.6 4.1 1.7 7.9 1.6 6.1 Q or Q UNIT ns Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 7 SN74LVC1G74 www.ti.com SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 6.8 Operating Characteristics TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 35 35 37 40 f = 10 MHz UNIT pF 6.9 Typical Characteristics 14 10 12 VCC = 3 V, TA = 25°C tpd – Propagation Delay Time – ns tpd – Propagation Delay Time – ns VCC = 3 V, TA = 25°C One Output Switching 10 8 6 4 2 One Output Switching 8 6 4 2 0 50 100 150 200 250 300 0 CL – Load Capacitance – pF Figure 6-1. Propagation Delay (Low to High Transition) vs Load Capacitance 8 50 100 150 200 250 300 CL – Load Capacitance – pF Figure 6-2. Propagation Delay (High to Low Transition) vs Load Capacitance Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 SN74LVC1G74 www.ti.com SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 7 Parameter Measurement Information VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL tPLZ VLOAD/2 VM tPZH VM VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VOH Output VM tPZL tPHL VM VI Output Control VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 7-1. Load Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 9 SN74LVC1G74 www.ti.com SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 8 Detailed Description 8.1 Overview This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 8.2 Functional Block Diagram PRE 7 1 CLK C C C 5 Q TG C C C C D 2 TG TG TG 3 C CLR Q C C 6 8.3 Feature Description • • • Allow down voltage translation – 5-V to 3.3-V – 5.0-V to 1.8-V – 3.3-V to 1.8-V Inputs accept voltage levels up to 5.5-V Ioff Feature – Can prevent backflow current that can damage device when powered down 8.4 Device Functional Modes Table 8-1. Function Table INPUTS (1) 10 OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 SN74LVC1G74 www.ti.com SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The 330 Ω resistor and 22 pF capacitor shown in Figure 9-1 produce enough delay to meet the hold time requirement of the D input. To calculate the delay for a particular RC combination, use Equation 1. The delay with this RC combination is 5.03 ns tdelay = −RC ln(0.5) ≈ 0.693 RC (1) To ensure proper operation, check that the transition time of the RC circuit meets the transition time requirements of the device inputs listed in the Recommended Operating Conditions table. Transition time for an RC can be approximated with Equation 2. tt≈ 2.2 RC (2) 9.2 Typical Power Button Circuit VCC VCC 0.1 F VCC 0.1 F 10 k 1A 1
F 1Y VCC 330  22 pF 20 k VCC D PRE Q CLR GND 2A 1 F CLK Q MCU 2Y SN74LVC2G17 Figure 9-1. Device Power Button Circuit Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 11 SN74LVC1G74 www.ti.com SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. Outputs can be combined to produce higher drive but the high drive will also create faster edges into light loads so routing and load conditions should be considered to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions: • For rise time and fall time specifications, see (Δt/ΔV) in the Recommended Operating Conditions table. • For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table. • Inputs are overvoltage tolerant allowing them to go as high as 5.5-V at any valid VCC. 2. Recommend Output Conditions: • Load currents should not exceed 50-mA per output and 100-mA total for the part. • Series resistors on the output may be used if the user desires to slow the output edge signal or limit the output current. 9.2.3 Application Curves 60 40 100 TA = 25°C, VCC = 3 V, VIH = 3 V, VIL = 0 V, All Outputs Switching 80 TA = 25°C, VCC = 3 V, VIH = 3 V, VIL = 0 V, All Outputs Switching 60 0 I OL – mA I OH – mA 20 –20 40 –40 20 –60 0 –80 –100 –1 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 –20 –0.2 0.0 VOH – V Figure 9-2. Output Current Drive vs HIGH-level Output Voltage 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VOL – V Figure 9-3. Output Current Drive vs LOW-level Output Voltage 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommonded Operating Conditions table. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended and if there are multiple VCC terminals then .01-μF or .022-μF capacitors are recommended for each power terminal. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 SN74LVC1G74 www.ti.com SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 11-1 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled. 11.2 Layout Example Vcc Unused Input Input Output Unused Input Output Input Figure 11-1. Layout Diagram Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 13 SN74LVC1G74 www.ti.com SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks NanoFree™ is a trademark of Texas Instruments. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 PACKAGE OPTION ADDENDUM www.ti.com 26-Jul-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LVC1G74DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 N74 Z SN74LVC1G74DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (N74J, N74Q, N74R) SN74LVC1G74DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 N74R SN74LVC1G74DCUT ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (N74J, N74Q, N74R) SN74LVC1G74DQER ACTIVE X2SON DQE 8 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 DP SN74LVC1G74RSE2 ACTIVE UQFN RSE 8 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 DP SN74LVC1G74RSER ACTIVE UQFN RSE 8 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 DP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of