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SN74LVC1G97
SCES416N – DECEMBER 2002 – REVISED JANUARY 2017
SN74LVC1G97 Configurable Multiple-Function Gate
1 Features
3 Description
•
The SN74LVC1G97 device features configurable
multiple functions. The output state is determined by
eight patterns of 3-bit input. The user can choose the
logic functions MUX, AND, OR, NAND, NOR,
inverter, and noninverter. All inputs can be connected
to VCC or GND.
1
•
•
•
•
•
•
•
•
•
•
ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to VCC
Max tpd of 6.3 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Choose From Nine Specific Logic Functions
This configurable multiple-function gate is designed
for 1.65-V to 5.5-V VCC operation.
This device functions as an independent gate, but
because of Schmitt action, it may have different input
threshold levels for positive-going (VT+) and negativegoing (VT–) signals.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as
the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
Barcode Scanners
Cable Solutions
E-Books
Embedded PCs
Field Transmitter: Temperature or Pressure
Sensors
Fingerprint Biometrics
HVAC: Heating, Ventilating, and Air Conditioning
Network-Attached Storage (NAS)
Server Motherboards and PSUs
Software Defined Radios (SDR)
TVs: High Definition (HDTV), LCD, and Digital
Video Communications Systems
Wireless Data Access Cards, Headsets,
Keyboard, Mouse, and LAN Cards
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1G97DBV
SOT-23 (6)
2.90 mm × 1.60 mm
SN74LVC1G97DCK
SC70 (6)
2.00 mm × 1.25 mm
SN74LVC1G97DRL
SN74LVC1G97DRY
1.60 mm × 1.20 mm
SOT (6)
SN74LVC1G97DSF
SN74LVC1G97YZP
1.45 mm × 1.00 mm
1.00 mm × 1.00 mm
DSBGA (6)
1.41 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
In0
3
4
1
Y
In1
In2
6
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G97
SCES416N – DECEMBER 2002 – REVISED JANUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
6
6
6
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (June 2015) to Revision N
Page
•
Changed body size for SN74LVC1G97DRY to 1.45 mm × 1.00 mm..................................................................................... 1
•
Changed body size for SN74LVC1G97DSF to 1.00 mm × 1.00 mm ..................................................................................... 1
•
Added Junction temperature, TJ in Absolute Maximum Ratings ........................................................................................... 4
•
Added Operating free-air temperature, TA for BGA package in Recommended Operating Conditions ................................ 4
•
Added Receiving Notification of Documentation Updates section ....................................................................................... 14
Changes from Revision L (December 2013) to Revision M
•
Page
Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................................... 1
Changes from Revision K (October 2011) to Revision L
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Updated Ioff in Features .......................................................................................................................................................... 1
•
Updated operating temperature range. .................................................................................................................................. 4
2
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SCES416N – DECEMBER 2002 – REVISED JANUARY 2017
5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
(Top View)
YZP Package
6-Pin DSBGA
(Bottom View)
In1
1
6
In2
GND
2
5
VCC
In0
3
4
Y
Not to scale
DCK Package
6-Pin SC70
(Top View)
1
2
C
In0
Y
B
GND
VCC
A
In1
In2
Not to scale
In1
1
6
In2
GND
2
5
VCC
In0
3
4
Y
DRY Package
6-Pin SON
(Top View)
Not to scale
DRL Package
6-Pin SOT
(Top View)
In1
1
6
In2
GND
2
5
VCC
In0
3
4
Y
In1
1
6
In2
GND
2
5
VCC
In0
3
4
Y
Not to scale
DSF Package
6-Pin SON
(Top View)
Not to scale
In1
1
6
In2
GND
2
5
VCC
In0
3
4
Y
Not to scale
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DCT, DCU, DRY
YZP
In0
3
C1
I
Input 0
In1
1
A1
I
Input 1
In2
6
A2
I
Input 2
GND
2
B1
—
Ground
VCC
5
B2
—
Power
Y
4
C2
O
Output
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SCES416N – DECEMBER 2002 – REVISED JANUARY 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0 V
–50
mA
IOK
Output clamp current
VO < 0 V
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101\ (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See
(1)
Operating
MIN
MAX
1.65
5.5
UNIT
VCC
Supply voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
Data retention only
1.5
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current
–8
–16
VCC = 3 V
Low-level output current
–32
VCC = 1.65 V
4
VCC = 2.3 V
8
16
VCC = 3 V
(1)
4
Operating free-air temperature
mA
24
VCC = 4.5 V
TA
mA
–24
VCC = 4.5 V
IOL
V
32
BGA package
–40
85
All other packages
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74LVC1G97
THERMAL METRIC (1)
RθJA
(1)
DBV (SOT-23)
DCK (SC70)
DRL (SOT)
YZP (DSBGA)
6 PINS
6 PINS
6 PINS
6 PINS
165
259
142
123
Junction-to-ambient thermal resistance
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VT+
Positive-going input
threshold voltage
VT–
Negative-going input
threshold voltage
ΔVT
Hysteresis (VT+ – VT–)
VOH
–40°C TO +125°C
MAX
MIN
MAX
1.16
0.79
1.16
1.11
1.56
1.11
1.56
3V
1.5
1.87
1.5
1.87
4.5 V
2.16
2.74
2.16
2.74
5.5 V
2.61
3.33
2.61
3.33
1.65 V
0.35
0.62
0.35
0.62
2.3 V
0.58
0.87
0.58
0.87
3V
0.84
1.19
0.84
1.19
4.5 V
1.41
1.9
1.41
1.9
5.5 V
1.87
2.29
1.87
2.29
1.65 V
0.3
0.62
0.3
0.62
2.3 V
0.4
0.8
0.4
0.8
3V
0.53
0.87
0.53
0.87
4.5 V
0.71
1.04
0.71
1.04
0.71
1.11
0.71
1.11
VCC – 0.1
VCC – 0.1
1.65 V
1.2
1.2
IOH = –8 mA
2.3 V
1.9
1.9
2.4
2.4
2.3
2.3
IOH = –16 mA
TYP (1)
0.79
IOH = –4 mA
3V
4.5 V
IOL = 100 µA
1.65 V to 5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
0.4
0.45
0.55
0.55
0.55
0.58
IOL = 16 mA
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND, IO = 0
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
CI
VI = VCC or GND
V
V
V
3.8
3V
IOL = 32 mA
II
3.8
UNIT
V
IOH = –32 mA
IOL = 24 mA
(1)
TYP (1)
2.3 V
1.65 V to 5.5 V
IOH = –24 mA
VOL
MIN
1.65 V
5.5 V
IOH = –100 µA
–40°C TO +85°C
4.5 V
V
0 to 5.5 V
±5
±5
µA
0
±10
±10
µA
1.65 V to 5.5 V
10
10
µA
3 V to 5.5 V
500
500
µA
3.3 V
3.5
3.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
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6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
–40°C TO 85°C
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
Any In
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.2
14.4
2
8.3
1.5
6.3
1.1
5.1
UNIT
ns
6.7 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
–40°C TO 125°C
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
Any In
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.2
16.4
2
9.3
1.5
7.3
1.1
6.1
UNIT
ns
6.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
22
23
23
26
UNIT
pF
6.9 Typical Characteristics
Power Dissipation Capacitance (pF)
26.5
26
25.5
25
24.5
24
23.5
23
22.5
22
21.5
0
1
2
3
4
5
6
Power Supply Voltage (V)
Figure 1. Power Dissipation Capacitance vs Power Supply Voltage
6
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + VD
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH − VD
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G97 device features configurable multiple functions. The output state is determined by eight
patterns of 3-bit input. The user can choose variations of common logic functions, like AND, OR, and NOT.
All inputs can be connected to VCC or GND.
This device functions as an independent gate, but because of Schmitt action, it may have different input
threshold levels for positive-going (VT+) and negative-going (VT–) signals.
This device is fully-specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
In0
3
4
1
Y
In1
In2
6
8.3 Feature Description
The SN74LVC1G97 device has a wide operating VCC range of 1.65 V to 5.5 V, which allows use in a broad
range of systems. The 5.5-V I/Os allow down translation and also allow voltages at the inputs when VCC = 0 V.
8.4 Device Functional Modes
Table 1 shows the functional modes of SN74LVC1G97.
Table 1. Function Table
INPUTS
8
OUTPUT
In2
In1
In0
Y
L
L
L
L
L
L
H
L
L
H
L
H
L
H
H
H
H
L
L
L
H
L
H
H
H
H
L
L
H
H
H
H
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Table 2. Function Selection Table
LOGIC FUNCTION
FIGURE NUMBER
2-to-1 data selector
Figure 3
2-input AND gate
Figure 4
2-input OR gate with one inverted input
Figure 5
2-input NAND gate with one inverted input
Figure 5
2-input AND gate with one inverted input
Figure 6
2-input NOR gate with one inverted input
Figure 6
2-input OR gate
Figure 7
Inverter
Figure 8
Noninverted buffer
Figure 9
VCC
A/B
A
A
Y
B
B
1
6
2
5
3
4
A/B
Y
GND
Figure 3. 2-to-1 Data Selector
VCC
A
Y
B
B
1
6
2
5
3
4
A
Y
GND
Figure 4. 2-Input AND Gate
VCC
A
Y
B
A
Y
B
B
1
6
2
5
3
4
A
Y
GND
Figure 5. 2-Input OR Gate With One Inverted Input
2-Input NAND Gate With One Inverted Input
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VCC
A
Y
B
B
A
Y
B
1
6
2
5
3
4
A
Y
GND
Figure 6. 2-Input AND Gate With One Inverted Input
2-Input NOR Gate With One Inverted Input
VCC
A
Y
B
B
1
6
2
5
3
4
A
Y
GND
Figure 7. 2-Input OR Gate
VCC
A
Y
1
6
2
5
3
4
A
Y
GND
Figure 8. Inverter
VCC
A
A
Y
1
6
2
5
3
4
Y
GND
Figure 9. Noninverted Buffer
10
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Validate and test
the design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G97 device offers flexible configuration for many design applications. This example describes
basic power sequencing using the AND gate configuration. Power sequencing is often used in applications that
require a processor or other delicate device with specific voltage timing requirements in order to protect the
device from malfunctioning.
VCC = 5 V
EN
A
Y
B
Temperature
Sensor
MCU
(MSP43x)
VO
Figure 10. Simplified Application
9.2 Typical Application
LVC1G97
A
VCC = 5 V
VCC
GND
EN
B
Y
MCU
(MSP43x)
Temperature
Sensor
VO
Figure 11. Typical Application
9.2.1 Design Requirements
•
•
•
Recommended input conditions:
– For rise time and fall time specifications, see Δt/Δv in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs and outputs are overvoltage tolerant and can therefore go as high as 5.5 V at any valid VCC.
Recommended output conditions:
– Load currents must not exceed ±50 mA.
Frequency selection criterion:
– Figure 12 illustrates the effects of frequency on output current.
– Added trace resistance and capacitance can reduce maximum frequency capability. Follow the layout
practices listed in the Layout section.
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11
SN74LVC1G97
SCES416N – DECEMBER 2002 – REVISED JANUARY 2017
www.ti.com
Typical Application (continued)
9.2.2 Detailed Design Procedure
The SN74LVC1G97 device uses CMOS technology and has balanced output drive. Avoid bus contentions
that can drive currents that can exceed maximum limits.
The SN74LVC1G97 allows for performing logical Boolean functions with digital signals. Maintain input signals
as close as possible to either 0 V or VCC for optimal operation.
9.2.3 Application Curve
5
Signal (V)
4
3
2
Vin
1
Vout
0
0
1
2
3
4
5
6
7
Time (ns)
8
9
10
C001
Figure 12. Simulated Input-to-Output Voltage Response Showing Propagation Delay at V CC = 5 V
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Recommended Operating Conditions table.
To prevent power disturbance, ensure good bypass capacitance for each VCC terminal. For devices with a singlesupply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual
supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. Place the bypass capacitor as close to the power
terminal as possible for best results.
12
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Product Folder Links: SN74LVC1G97
SN74LVC1G97
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SCES416N – DECEMBER 2002 – REVISED JANUARY 2017
11 Layout
11.1 Layout Guidelines
When using multiple-bit logic devices, inputs must never float.
In many cases, functions (or parts of functions) of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or when only 3 of the 4 buffer gates are used. Such input pins must
not be left unconnected, because the undefined voltages at the outside connections result in undefined
operational states. Figure 13 specifies the rules that must be observed under all circumstances. All unused
inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic
level that must be applied to any particular unused input depends on the function of the device. Generally they
are tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float
outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it disables the output section
of the part when asserted, which does not disable the input section of the I/Os. Therefore, the I/Os cannot float
when disabled.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 13. Layout Diagrams
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Product Folder Links: SN74LVC1G97
13
SN74LVC1G97
SCES416N – DECEMBER 2002 – REVISED JANUARY 2017
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• Selecting the Right Texas Instruments Signal Switch, SZZA030
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC1G97DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(C975, C97K, C97R)
Samples
SN74LVC1G97DBVRE4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(C975, C97K, C97R)
Samples
SN74LVC1G97DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(C975, C97K, C97R)
Samples
SN74LVC1G97DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(C975, C97K, C97R)
Samples
SN74LVC1G97DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(C975, C97K, C97R)
Samples
SN74LVC1G97DCK3
ACTIVE
SC70
DCK
6
3000
RoHS &
Non-Green
SNBI
Level-1-260C-UNLIM
-40 to 125
CSZ
Samples
SN74LVC1G97DCKR
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CS5, CSF, CSJ, CS
K, CSR)
Samples
SN74LVC1G97DCKRE4
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CS5
Samples
SN74LVC1G97DCKRG4
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CS5
Samples
SN74LVC1G97DCKT
ACTIVE
SC70
DCK
6
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CS5, CSF, CSJ, CS
K, CSR)
Samples
SN74LVC1G97DCKTG4
ACTIVE
SC70
DCK
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CS5
Samples
SN74LVC1G97DRLR
ACTIVE
SOT-5X3
DRL
6
4000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(1K4, CS7, CSR)
Samples
SN74LVC1G97DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CS
Samples
SN74LVC1G97DSFR
ACTIVE
SON
DSF
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CS
Samples
SN74LVC1G97YZPR
ACTIVE
DSBGA
YZP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
CSN
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Aug-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of