SN74LVC1G97IDCKREP

       SCES461B − JUNE 2003 − REVISED FEBRUARY 2005 D Controlled Baseline D D D D D D D − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 6.3 ns at 3.3 V Low Power Consumption, 10-µA Max ICC D ±24-mA Output Drive at 3.3 V D Ioff Supports Partial-Power-Down Mode Operation D Latch-Up Performance Exceeds 100 mA D D Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) Choose From Nine Specific Logic Functions DCK PACKAGE (TOP VIEW) † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. In1 GND In0 1 6 2 5 4 3 In2 VCC Y description/ordering information This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G97 features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All inputs can be connected to VCC or GND. This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT−) signals. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 85°C SOT (SC-70) − DCK Tape and reel SN74LVC1G97IDCKREP CSR ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2005, Texas Instruments Incorporated    ! "#$ !  %#&'" ($) (#"! "  !%$""! %$ *$ $!  $+! !#$! !(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($ $!.  '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
       SCES461B − JUNE 2003 − REVISED FEBRUARY 2005 FUNCTION TABLE INPUTS In0 OUTPUT Y L L L L H L H L H H H H In2 In1 L L L L H L L L H L H H H H L L H H H H logic diagram (positive logic) In0 3 4 In1 In2 1 6 FUNCTION SELECTION TABLE LOGIC FUNCTION 2 FIGURE NO. 2-to-1 data selector 1 2-input AND gate 2 2-input OR gate with one inverted input 3 2-input NAND gate with one inverted input 3 2-input AND gate with one inverted input 4 2-input NOR gate with one inverted input 4 2-input OR gate 5 Inverter 6 Noninverted buffer 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Y 
       SCES461B − JUNE 2003 − REVISED FEBRUARY 2005 logic configurations VCC VCC A/B A A Y B B 1 6 2 5 3 4 A/B A Y B B Y GND 1 6 2 5 3 4 A Y GND Figure 1. 2-to-1 Data Selector Figure 2. 2-Input AND Gate VCC A VCC A B B A Y Y Y B B 1 6 2 5 3 4 A B A Y Y B 1 6 2 5 3 4 A Y GND GND Figure 3. 2-Input OR Gate With One Inverted Input 2-Input NAND Gate With One Inverted Input Figure 4. 2-Input AND Gate With One Inverted Input 2-Input NOR Gate With One Inverted Input VCC VCC A Y 1 B B 6 2 5 3 4 A A Y Y 1 6 2 5 3 4 A Y GND GND Figure 6. Inverter Figure 5. 2-Input OR Gate VCC A A Y 1 6 2 5 3 4 Y GND Figure 7. Noninverted Buffer POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
       SCES461B − JUNE 2003 − REVISED FEBRUARY 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) Operating VCC Supply voltage VI VO Input voltage Data retention only Output voltage VCC = 1.65 V VCC = 2.3 V IOH MAX 5.5 VCC = 3 V VCC = 2.3 V 0 5.5 V 0 VCC −4 V −8 mA −24 −32 4 8 16 Low-level output current UNIT V 1.5 −16 High-level output current VCC = 4.5 V VCC = 1.65 V IOL MIN 1.65 VCC = 3 V 24 VCC = 4.5 V 32 mA TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
       SCES461B − JUNE 2003 − REVISED FEBRUARY 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ Positive-going input threshold voltage VT− Negative-going input threshold voltage ∆VT Hysteresis (VT+ − VT−) MIN 1.65 V 0.79 1.16 2.3 V 1.11 1.56 3V 1.5 1.87 4.5 V 2.16 2.74 5.5 V 2.61 3.33 1.65 V 0.35 0.62 2.3 V 0.58 0.87 3V 0.84 1.19 4.5 V 1.41 1.9 5.5 V 1.87 2.29 1.65 V 0.3 0.62 VOH 0.4 0.8 3V 0.53 0.87 4.5 V 0.71 1.04 0.71 1.11 1.65 V to 5.5 V 1.65 V IOH = −8 mA IOH = −16 mA 2.3 V 4.5 V IOH = −32 mA IOL = 100 mA IOL = 4 mA IOL = 8 mA IOL = 16 mA VI = 5.5 V or GND VI or VO = 5.5 V ICC VI = 5.5 V or GND, ∆ICC One input at VCC − 0.6 V, 3.8 0.1 1.65 V 0.45 2.3 V 0.3 4.5 V 0.55 ±5 mA ±10 mA 1.65 V to 5.5 V 10 mA 3 V to 5.5 V 500 mA 0 3.3 V POST OFFICE BOX 655303 V 0.55 0 to 5.5 V Ci VI = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. V 2.3 0.4 IO = 0 Other inputs at VCC or GND V V 3V IOL = 32 mA II Ioff V 1.9 1.65 V to 5.5 V IOL = 24 mA UNIT VCC − 0.1 1.2 2.4 3V IOH = −24 mA VOL MAX 2.3 V 5.5 V IOH = −100 mA IOH = −4 mA TYP† VCC • DALLAS, TEXAS 75265 3.5 pF 5 
       SCES461B − JUNE 2003 − REVISED FEBRUARY 2005 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 8) PARAMETER tpd FROM (INPUT) TO (OUTPUT) Any In Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 3.2 14.4 2 8.3 1.5 6.3 1.1 5.1 UNIT ns operating characteristics, TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS f = 10 MHz POST OFFICE BOX 655303 VCC = 1.8 V TYP VCC = 2.5 V TYP 22 • DALLAS, TEXAS 75265 23 VCC = 3.3 V TYP 23 VCC = 5 V TYP 26 UNIT pF 
       SCES461B − JUNE 2003 − REVISED FEBRUARY 2005 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 8. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LVC1G97IDCKREP ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CSR V62/03642-01XE ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CSR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of