SN74LVC1G99DCTR

SN74LVC1G99 www.ti.com SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013 Ultra-Configurable Multiple-Function Gate With 3-State Output Check for Samples: SN74LVC1G99 FEATURES DESCRIPTION • The SN74LVC1G99 device is operational from 1.65 V to 5.5 V. 1 2 • • • • • • • • • • • Available in Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Supports Down Translation to VCC Max tpd of 6.7 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Offers Nine Different Logic Functions in a Single Package Ioff Supports Live Insertion, Partial-PowerDown Mode, and Back-Drive Protection Input Hysteresis Allows for Slow Input Transition Time and Better Noise Immunity at Input Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DCT PACKAGE (TOP VIEW) The SN74LVC1G99 device features configurable multiple functions with a 3-state output. The output is disabled when the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input. The user can choose logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND. This device functions as an independent inverter, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negativegoing (VT–) signals. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. NanoFree™ package technologies are a major breakthrough in IC packaging concepts, using the die as the package. DCU PACKAGE (TOP VIEW) OE 1 8 VCC A 2 7 Y B 3 6 D GND 4 5 C OE A B GND 1 8 2 7 3 6 4 5 YZP PACKAGE (BOTTOM VIEW) VCC Y D C GND B A OE 4 5 3 6 2 7 1 8 C D Y VCC See mechanical drawings for dimensions. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2013, Texas Instruments Incorporated SN74LVC1G99 SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Function Table INPUTS OUTPUT OE D C B A L L L L L Y L L L L L H H L L L H L L L L L H H H L L H L L L L L H L H L L L H H L H L L H H H H L H L L L H L H L L H L L H L H L H L H L H H L L H H L L H L H H L H H L H H H L L L H H H H L H H or L H or L H or L H or L Z Logic Diagram (Positive Logic) OE A B 1 2 3 7 5 Y C D 2 6 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G99 SN74LVC1G99 www.ti.com SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013 Function Selection Table PRIMARY FUNCTION COMPLEMENTARY FUNCTION PAGE 3-state buffer 3 3-state inverter 3 3-state 2-in-1 data selector MUX 4 3-state 2-in-1 data selector MUX, inverted out 4 3-state 2-input AND 3-state 2-input NOR, both inputs inverted 5 3-state 2-input AND, one input inverted 3-state 2-input NOR, one input inverted 5 3-state 2-input AND, both inputs inverted 3-state 2-input NOR 5 3-state 2-input NAND 3-state 2-input OR, both inputs inverted 6 3-state 2-input NAND, one input inverted 3-state 2-input OR, one input inverted 6 3-state 2-input NAND, both inputs inverted 3-state 2-input OR 6 3-state 2-input XOR 7 3-state 2-input XNOR 3-state 2-input XOR, one input inverted 7 3-State Buffer Functions Available OE Input FUNCTION 3-state buffer OE L Y A B C D Input H or L L L H or L Input H L L H Input L H L Input H H H or L L Input H or L L H Input L L H or L Input Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G99 3 SN74LVC1G99 SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013 www.ti.com 3-State Inverter Functions Available OE Input FUNCTION Y OE 3-state buffer A B C D Input H or L L H X Input H H L H Input H H L Input L H H or L L Input H or L H H Input H H H or L Input L 3-State MUX Functions Available A/B A/B Input 1 Input 1 Y Input 2 FUNCTION Y Input 2 A B C D 3-state 2-to-1, data selector MUX Input 1 Input 2 Input 1 or Input 2 L 3-state 2-to-1, data selector MUX Input 2 Input 1 Input 2 or Input 1 L Input 1 Input 2 Input 1 or Input 2 H Input 2 Input 1 Input 2 or Input 1 H 3-state 2-to-1, data selector MUX, inverted out 3-state 2-to-1, data selector MUX, inverted out 4 OE L Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G99 SN74LVC1G99 www.ti.com SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013 3-State AND/NOR/OR Functions Available OE OE Input 1 Input 1 Y Y Input 2 Input 2 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state AND 3-state NOR 2 3-state AND 3-state NOR OE A B C D L Input 1 Input 2 L L Input 2 Input 1 L B C D Input 2 L Input 1 L H Input 1 Input 2 H D L OE OE Input 1 Input 1 Y Y Input 2 Input 2 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state AND 3-state NOR 2 3-state AND 3-state NOR OE L OE A OE Input 1 Input 1 Y Input 2 Y Input 2 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state AND 3-state NOR 2 3-state AND 3-state NOR OE OE L A B C Input 1 L Input 2 L H Input 2 Input 1 H OE Input 1 Y Input 2 Input 1 Y Input 2 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state AND, both inverted inputs 3-state NOR 2 3-state AND, both inverted inputs 3-state NOR OE L A B C D Input 1 H Input 2 H Input 2 H Input 1 H Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G99 5 SN74LVC1G99 SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013 www.ti.com 3-State NAND/OR Functions Available OE OE Input 1 Y Input 2 Input 1 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state NAND 3-state OR 2 3-state NAND 3-state OR OE A B C D L Input 1 Input 2 H L Input 2 Input 1 H B C D Input 2 L Input 1 H H Input 1 Input 2 L L OE OE Input 1 Y Input 2 Input 1 Y Input 2 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state NAND 3-state OR 2 3-state NAND 3-state OR OE L OE A OE Input 1 Y Input 2 Input 1 Y Input 2 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state NAND 3-state OR 2 3-state NAND 3-state OR OE L OE A B C D Input 1 L Input 2 H H Input 2 Input 1 L OE Input 1 Y Input 2 6 Y Input 2 Input 1 Y Input 2 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state NAND 3-state OR 2 3-state NAND 3-state OR OE L A B C D Input 1 H Input 2 L Input 2 H Input 1 L Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G99 SN74LVC1G99 www.ti.com SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013 3-State XOR/XNOR Functions Available OE Input 1 Y Input 2 FUNCTION OE 3-state XOR L A B C D Input 1 H or L L Input 2 Input 2 H or L L Input 1 H or L Input 1 H Input 2 H or L Input 2 H Input 1 L H Input 1 Input 2 L H Input 2 Input 1 OE Input 1 Y Input 2 FUNCTION OE A B C D 3-state XOR L H L Input 1 Input 2 OE Input 1 Y Input 2 FUNCTION OE A B C D 3-state XOR L H L Input 1 Input 2 OE Input 1 Y Input 2 FUNCTION 3-state XNOR 3-state XNOR OE L A B C D H L Input 1 Input 2 H L Input 2 Input 1 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G99 7 SN74LVC1G99 SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range DCT package 220 DCU package 227 YZP package (1) (2) (3) (4) °C/W 102 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) Operating MIN MAX 1.65 5.5 UNIT VCC Supply voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V Data retention only 1.5 VCC = 1.65 V –4 VCC = 2.3 V IOH High-level output current –8 –16 VCC = 3 V –32 VCC = 1.65 V 4 VCC = 2.3 V Low-level output current Δt/Δv Input transition rise or fall rate (1) 8 8 16 VCC = 3 V mA 24 VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V mA –24 VCC = 4.5 V IOL V ns/V 5 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G99 SN74LVC1G99 www.ti.com SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VT+ Positivegoing input threshold voltage VT– Negativegoing input threshold voltage ΔVT Hysteresis (VT+ – VT–) VOH TYP (1) –40°C to 125°C MAX MIN MAX 0.79 1.26 0.79 1.26 2.3 V 1.11 1.66 1.11 1.66 3V 1.5 1.97 1.5 1.97 4.5 V 2.16 2.84 2.16 2.84 5.5 V 2.61 3.43 2.61 3.43 1.65 V 0.39 0.72 0.39 0.72 2.3 V 0.58 0.97 0.58 0.97 3V 0.84 1.24 0.84 1.24 4.5 V 1.41 1.89 1.41 1.89 5.5 V 1.87 2.39 1.87 2.39 1.65 V 0.37 0.72 0.37 0.72 2.3 V 0.48 0.87 0.48 0.87 3V 0.56 0.97 0.56 0.97 4.5 V 0.71 1.14 0.71 1.14 1.21 0.71 1.21 5.5 V 0.71 IOH = –100 µA VCC – 0.1 VCC – 0.1 IOH = –4 mA 1.65 V 1.2 1.2 IOH = –8 mA 2.3 V 1.9 1.9 2.4 2.4 2.3 2.3 3.8 3.8 3V IOH = –24 mA TYP (1) 1.65 V 1.65 V to 5.5 V IOH = –16 mA VOL –40°C to 85°C MIN 4.5 V IOL = 100 µA 1.65 V to 5.5 V 0.1 0.1 IOL = 4 mA 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 0.4 0.4 3V IOL = 24 mA V V V V IOH = –32 mA IOL = 16 mA UNIT V 0.55 0.55 IOL = 32 mA 4.5 V 0.55 0.55 II VI = 5.5 V or GND 0 V to 5.5 V ±5 ±5 µA Ioff VI or VO = 5.5 V 0V ±10 ±10 µA IOZ VO = VCC or GND 1.65 V to 5.5 V ±10 ±10 µA ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 10 µA ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 500 µA Ci VI = VCC or GND 3.3 V 3.5 3.5 pF Co VO = VCC or GND 3.3 V 6 6 pF (1) TA = 25°C Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G99 9 SN74LVC1G99 SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013 www.ti.com Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) SN74LVC1G99 –40°C to 85°C PARAMETER tpd FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX A 4.5 30.1 2.5 11.3 1.8 7.5 1.3 4.8 B 4.4 28.3 2.4 10.8 1.8 7.2 1.3 4.7 4.4 29.1 2.4 11.7 1.9 7.6 1.3 5 Y C D ns 4.3 25.1 2.4 10.2 1.7 6.7 1.3 4.5 ten OE Y 3.4 24.7 2.1 10 1.3 5.8 1 3.8 ns tdis OE Y 4 15.5 2.7 7.5 3.5 7 2 5.5 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) SN74LVC1G99 –40°C to 85°C PARAMETER tpd FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX A 4.6 30.8 2.6 11.7 2.4 8.4 1.8 5.5 B 4.6 28.9 2.6 11.3 2.3 8.2 1.8 5.4 4.4 29.8 2.5 12.3 2.5 8.6 1.8 5.7 Y C D ns 4.3 25.7 2.5 10.7 2.4 7.6 1.6 5.2 ten OE Y 4.2 25.2 2.4 11.3 2 7 1.7 4.7 ns tdis OE Y 3.7 15 2 5.8 2.1 5.6 1 4.5 ns Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN74LVC1G99 –40°C to 125°C PARAMETER tpd FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX A 4.6 32.8 2.6 13.7 2.4 10.4 1.8 6.9 B 4.6 30.9 2.6 13.3 2.3 10.2 1.8 6.8 4.4 31.8 2.4 14.3 2.5 10.6 1.8 7.2 C Y D ns 4.3 27.7 2.5 12.7 2.4 9.5 1.6 6.5 ten OE Y 4.2 27.2 2.4 13.3 2.0 9.0 1.7 6.0 ns tdis OE Y 3.7 17.0 2.0 7.3 2.1 7.4 1.0 5.6 ns Operating Characteristics TA = 25°C PARAMETER Cpd 10 Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 19 20 22 27 Submit Documentation Feedback UNIT pF Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G99 SN74LVC1G99 www.ti.com SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013 Parameter Measurement Information VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MW 1 MW 1 MW 1 MW 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G99 11 SN74LVC1G99 SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013 www.ti.com Parameter Measurement Information (continued) VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 12 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G99 SN74LVC1G99 www.ti.com SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013 REVISION HISTORY Changes from Revision E (October 2007) to Revision F Page • Changed document template from TIMS format to DocZone format. .................................................................................. 1 • Changed 3-State Mux graphic to fix labeling error. .............................................................................................................. 4 Changes from Revision F (April 2011) to Revision G Page • Updated document to new TI data sheet format. ................................................................................................................. 1 • Updated Features. ................................................................................................................................................................ 1 • Added ESD warning. ............................................................................................................................................................ 2 • Updated operating temperature range. ................................................................................................................................. 8 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G99 13 PACKAGE OPTION ADDENDUM www.ti.com 29-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LVC1G99DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C99 (R, Z) SN74LVC1G99DCTRG4 ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C99 (R, Z) SN74LVC1G99DCTT ACTIVE SM8 DCT 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C99 (R, Z) SN74LVC1G99DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C99J, C99Q, C99R) SN74LVC1G99DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C99R SN74LVC1G99DCUT ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C99J, C99Q, C99R) SN74LVC1G99YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 DEN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of