SN74LVC1G99QDCURQ1

SN74LVC1G99-Q1 SCES828 – JUNE 2011 www.ti.com ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE WITH 3-STATE OUTPUT Check for Samples: SN74LVC1G99-Q1 FEATURES 1 • • • • • • Qualified for Automotive Applications Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Low Power Consumption, 15-μA Max ICC ±24-mA Output Drive at 3.3 V Offers Nine Different Logic Functions in a Single Package Ioff Supports Partial-Power-Down Mode Operation Input Hysteresis Allows for Slow Input Transition Time and Better Noise Immunity at Input • • DCU PACKAGE (TOP VIEW) OE A B GND 1 8 VCC 2 7 Y D C 3 6 4 5 DESCRIPTION/ORDERING INFORMATION The SN74LVC1G99-Q1 is operational from 1.65 V to 5.5 V. The SN74LVC1G99-Q1 features configurable multiple functions with a 3-state output. The output is disabled when the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input. The user can choose logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND. This device functions as an independent inverter, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT–) signals. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE –40°C to 125°C VSSOP – DCU (1) (2) (3) (1) (2) Reel of 3000 ORDERABLE PART NUMBER SN74LVC1G99QDCURQ1 TOP-SIDE MARKING (3) CAZ_ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DCU: The actual top-side marking has one additional character that designates the assembly/test site. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated SN74LVC1G99-Q1 SCES828 – JUNE 2011 www.ti.com FUNCTION TABLE INPUTS 2 OUTPUT OE D C B A L L L L L Y L L L L L H H L L L H L L L L L H H H L L H L L L L L H L H L L L H H L H L L H H H H L H L L L H L H L L H L L H L H L H L H L H H L L H H L L H L H H L H H L H H H L L L H H H H L H H or L H or L H or L H or L Z Copyright © 2011, Texas Instruments Incorporated SN74LVC1G99-Q1 SCES828 – JUNE 2011 www.ti.com LOGIC DIAGRAM (POSITIVE LOGIC) OE A B 1 2 3 7 5 Y C D 6 FUNCTION SELECTION TABLE PRIMARY FUNCTION COMPLEMENTARY FUNCTION PAGE 3-state buffer 3 3-state inverter 3 3-state 2-in-1 data selector MUX 4 3-state 2-in-1 data selector MUX, inverted out 4 3-state 2-input AND 3-state 2-input NOR, both inputs inverted 5 3-state 2-input AND, one input inverted 3-state 2-input NOR, one input inverted 5 3-state 2-input AND, both inputs inverted 3-state 2-input NOR 5 3-state 2-input NAND 3-state 2-input OR, both inputs inverted 6 3-state 2-input NAND, one input inverted 3-state 2-input OR, one input inverted 6 3-state 2-input NAND, both inputs inverted 3-state 2-input OR 6 3-state 2-input XOR 7 3-state 2-input XNOR 3-state 2-input XOR, one input inverted 7 3-STATE BUFFER FUNCTIONS AVAILABLE OE Input FUNCTION 3-state buffer Copyright © 2011, Texas Instruments Incorporated OE L Y A B C D Input H or L L L H or L Input H L L H Input L H L Input H H H or L L Input H or L L H Input L L H or L Input 3 SN74LVC1G99-Q1 SCES828 – JUNE 2011 www.ti.com 3-STATE INVERTER FUNCTIONS AVAILABLE OE Input FUNCTION Y OE 3-state buffer A B C D Input H or L L H X Input H H L H Input H H L Input L H H or L L Input H or L H H Input H H H or L Input L 3-STATE MUX FUNCTIONS AVAILABLE A/B A/B Input 1 Input 1 Y Input 2 FUNCTION Y Input 2 A B C D 3-state 2-to-1, data selector MUX Input 1 Input 2 Input 1 or Input 2 L 3-state 2-to-1, data selector MUX Input 2 Input 1 Input 2 or Input 1 L Input 1 Input 2 Input 1 or Input 2 H Input 2 Input 1 Input 2 or Input 1 H 3-state 2-to-1, data selector MUX, inverted out 3-state 2-to-1, data selector MUX, inverted out 4 OE L Copyright © 2011, Texas Instruments Incorporated SN74LVC1G99-Q1 SCES828 – JUNE 2011 www.ti.com 3-STATE AND/NOR/OR FUNCTIONS AVAILABLE OE OE Input 1 Input 1 Y NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state AND 3-state NOR 2 3-state AND 3-state NOR OE L OE A B C D L Input 1 Input 2 L L Input 2 Input 1 L B C D Input 2 L Input 1 L H Input 1 Input 2 H D OE Input 1 Input 1 Y Y Input 2 Input 2 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state AND 3-state NOR 2 3-state AND 3-state NOR OE L OE A OE Input 1 Input 1 Y Input 2 Y Input 2 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state AND 3-state NOR 2 3-state AND 3-state NOR OE Input 1 Input 2 OE L A B C Input 1 L Input 2 L H Input 2 Input 1 H OE Y Input 1 Y Input 2 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state AND, both inverted inputs 3-state NOR 2 3-state AND, both inverted inputs 3-state NOR Copyright © 2011, Texas Instruments Incorporated Y Input 2 Input 2 OE L A B C D Input 1 H Input 2 H Input 2 H Input 1 H 5 SN74LVC1G99-Q1 SCES828 – JUNE 2011 www.ti.com 3-STATE NAND/OR FUNCTIONS AVAILABLE OE OE Input 1 Y Input 2 Input 1 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state NAND 3-state OR 2 3-state NAND 3-state OR OE L OE A B C D L Input 1 Input 2 H L Input 2 Input 1 H B C D Input 2 L Input 1 H H Input 1 Input 2 L OE Input 1 Y Input 2 Input 1 Y Input 2 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state NAND 3-state OR 2 3-state NAND 3-state OR OE L OE A OE Input 1 Y Input 2 Input 1 Y Input 2 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state NAND 3-state OR 2 3-state NAND 3-state OR OE L OE A B C D Input 1 L Input 2 H H Input 2 Input 1 L OE Input 1 Y Input 2 6 Y Input 2 Input 1 Y Input 2 NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION 2 3-state NAND 3-state OR 2 3-state NAND 3-state OR OE L A B C D Input 1 H Input 2 L Input 2 H Input 1 L Copyright © 2011, Texas Instruments Incorporated SN74LVC1G99-Q1 SCES828 – JUNE 2011 www.ti.com 3-STATE XOR/XNOR FUNCTIONS AVAILABLE OE Input 1 Y Input 2 FUNCTION OE 3-state XOR L A B C D Input 1 H or L L Input 2 Input 2 H or L L Input 1 H or L Input 1 H Input 2 H or L Input 2 H Input 1 L H Input 1 Input 2 L H Input 2 Input 1 OE Input 1 Y Input 2 FUNCTION OE A B C D 3-state XOR L H L Input 1 Input 2 OE Input 1 Y Input 2 FUNCTION OE A B C D 3-state XOR L H L Input 1 Input 2 OE Input 1 Y Input 2 FUNCTION 3-state XNOR 3-state XNOR Copyright © 2011, Texas Instruments Incorporated OE L A B C D H L Input 1 Input 2 H L Input 2 Input 1 7 SN74LVC1G99-Q1 SCES828 – JUNE 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA (3) Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) DCU package –65 ±100 mA 227 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) Operating MIN MAX 1.65 5.5 UNIT VCC Supply voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V IOH High-level output current Data retention only 1.5 VCC = 1.65 V –4 VCC = 2.3 V –8 –16 VCC = 3 V –32 VCC = 1.65 V 4 VCC = 2.3 V Low-level output current Δt/Δv Input transition rise or fall rate (1) 8 8 16 VCC = 3 V mA 24 VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V mA –24 VCC = 4.5 V IOL V ns/V 5 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Copyright © 2011, Texas Instruments Incorporated SN74LVC1G99-Q1 SCES828 – JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ Positive-going input threshold voltage VT– Negativegoing input threshold voltage ΔVT Hysteresis (VT+ – VT–) VOH 1.65 V 0.79 1.26 2.3 V 1.11 1.66 3V 1.5 1.97 4.5 V 2.16 2.84 5.5 V 2.61 3.43 0.39 0.72 2.3 V 0.58 0.97 3V 0.84 1.24 4.5 V 1.41 1.89 5.5 V 1.87 2.39 1.65 V 0.37 0.72 2.3 V 0.48 0.87 3V 0.56 0.97 4.5 V 0.71 1.14 5.5 V 0.71 1.21 1.65 V 1.2 2.3 V 1.9 3V V 2.3 4.5 V IOL = 100 μA 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.35 3.8 V 0.45 3V IOL = 32 mA V V 1.65 V to 5.5 V IOL = 24 mA V 2.4 IOH = –32 mA IOL = 16 mA UNIT VCC – 0.1 IOH = –8 mA IOH = –24 mA MAX 1.65 V IOH = –4 mA IOH = –16 mA VOL MIN 1.65 V to 5.5 V IOH = –100 μA TYP (1) VCC 0.55 4.5 V 0.60 0 V to 5.5 V ±5 μA 0V ±10 μA 1.65 V to 5.5 V ±10 μA 1.65 V to 5.5 V 15 μA 500 μA II VI = 5.5 V or GND Ioff VI or VO = 5.5 V IOZ VO = VCC or GND ICC VI = 5.5 V or GND, IO = 0 ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND 3.3 V 3.5 pF Co VO = VCC or GND 3.3 V 6 pF (1) 3 V to 5.5 V TA = 25°C Copyright © 2011, Texas Instruments Incorporated 9 SN74LVC1G99-Q1 SCES828 – JUNE 2011 www.ti.com SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) VCC = 1.8 V ± 0.15 V TO (OUTPUT) VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX A 4.6 32.8 2.6 13.7 2.4 10.4 1.8 6.9 B 4.6 30.9 2.6 13.3 2.3 10.2 1.8 6.8 4.4 31.8 2.5 14.3 2.5 10.6 1.8 7.2 C Y D ns 4.3 27.7 2.5 12.7 2.4 9.6 1.6 6.5 ten OE Y 4.2 27.2 2.4 13.3 2 9 1.7 6.0 ns tdis OE Y 3.7 17 2 7.3 2.1 7.4 1 5.6 ns OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd 10 Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 19 20 22 27 UNIT pF Copyright © 2011, Texas Instruments Incorporated SN74LVC1G99-Q1 SCES828 – JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH VM VOL tPHL tPLZ VLOAD/2 VM tPZH VM VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VOH Output VM tPZL tPHL VM Output VI Output Control VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Copyright © 2011, Texas Instruments Incorporated 11 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LVC1G99QDCURQ1 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CAZR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of