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SN74LVC1GU04
SCES215Y – APRIL 1999 – REVISED DECEMBER 2017
SN74LVC1GU04 Single Inverter Gate
1 Features
3 Description
•
This single inverter gate is designed for 1.65-V to
5.5-V VCC operation.
1
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Unbuffered Output
Maximum tpd of 3.7 ns at 3.3 V
Low Power Consumption, 10-μA Maximum ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The SN74LVC1GU04 device contains one inverter
with an unbuffered output and performs the Boolean
function Y = A.
NanoFree package technology is a major
breakthrough in device packaging concepts, using the
die as the package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1GU04DBV
SOT-23 (5)
2.90 mm × 1.60 mm
SN74LVC1GU04DCK
SC70 (5)
2.00 mm × 1.25 mm
SN74LVC1GU04DRL
SOT-5X3 (5)
1.60 mm × 1.20 mm
SN74LVC1GU04DRY
SON (6)
1.45 mm × 1.00 mm
SN74LVC1GU04DSF
SON (6)
1.00 mm × 1.00 mm
SN74LVC1GU04YZP
DSBGA (5)
1.44 mm × 0.94 mm
SN74LVC1GU04YZV
DSBGA (4)
0.91 mm × 0.91 mm
2 Applications
SN74LVC1GU04DPW
X2SON (5)
0.80 mm × 0.80 mm
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
AV Receivers
Blu-ray Players and Home Theaters
DVD Recorders and Players
Desktop or Notebook PCs
Digital Radio or Internet Radio Players
Digital Video Cameras (DVC)
Embedded PCs
GPS: Personal Navigation Devices
Mobile Internet Devices
Network Projector Front-Ends
Portable Media Players
Pro Audio Mixers
Smoke Detectors
Solid-State Drive (SSD): Enterprise
High-Definition (HDTV)
Tablets: Enterprise
Audio Docks: Portable
DLP Front Projection Systems
DVR and DVS
Digital Picture Frame (DPF)
Digital Still Cameras
Logic Diagram (Positive Logic)
A
2
4
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1GU04
SCES215Y – APRIL 1999 – REVISED DECEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
5
5
5
6
6
7
7
7
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics: TA = –40°C to +85°C ......
Switching Characteristics: TA = –40°C to +125°C ....
Operating Characteristics..........................................
Typical Characteristic................................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision X (November 2017) to Revision Y
•
Page
Updated input voltage minimum from 0.5 V to –0.5 V in Absolute Maximum Ratings table.................................................. 5
Changes from Revision W (January 2016) to Revision X
Page
•
Changed values in the Thermal Information table to align with JEDEC standards................................................................ 6
•
Updated Feature Description to include more detailed information about specific device features. ..................................... 9
•
Changed Typical Application to oscillator circuit. ................................................................................................................. 11
•
Added DPW layout example................................................................................................................................................. 13
Changes from Revision V (November 2013) to Revision W
•
Page
Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Typical
Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section,
Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision U (June 2011) to Revision V
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Updated operating free-air temperature range in Recommended Operating Conditions table.............................................. 5
2
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SCES215Y – APRIL 1999 – REVISED DECEMBER 2017
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
N.C.
1
A
2
GND
3
DCK Package
5-Pin SC70
Top View
VCC
5
1
2
GND
3
A
2
GND
3
5
VCC
4
Y
YZV Package
4-Pin DSBGA
Top View
DRL Package
5-Pin SOT
Top View
A
1
Y
4
N.C.
N.C.
5
VCC
4
Y
A
A1
A2
VCC
GND
B1
B2
Y
DPW Package
5-Pin SON
Top View
GND
NC
A
VCC
Y
Pin Functions (1) (2)
PIN
I/O
DESCRIPTION
DBV, DRL,
DCK, DPW
YZV
A
2
A1
I
GND
3
B1
—
Ground
NC
1
–
—
Not connected
VCC
5
A2
—
Positive Supply
Y
4
B2
O
Output
NAME
(1)
(2)
Input
NC – No internal connection
See Mechanical, Packaging, and Orderable Information for dimensions
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DSF Package
6-Pin SON
Top View
N.C.
A
GND
1
6
2
5
3
4
DRY Package
6-Pin SON
Top View
VCC
N.C.
Y
N.C.
1
6
VCC
A
2
5
N.C.
GND
3
4
Y
YZP Package
6-Pin DSBGA
Top View
DNU
A1
A2
A
B1
B2
GND
C1
C2
VCC
Y
DNU – Do not use
Pin Functions (1) (2)
PIN
NAME
DSF, DRY
YZP
I/O
DESCRIPTION
A
2
B1
I
GND
3
C1
—
Ground
NC
1, 5
A1, B2
—
Not connected
VCC
6
A2
—
Positive Supply
Y
4
C2
O
Output
(1)
(2)
4
Input
NC – No internal connection
See Mechanical, Packaging, and Orderable Information for dimensions
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
–0.5
6.5
V
–0.5
VCC + 0.5
V
VI
Input voltage
VO
Voltage applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
150
°C
150
°C
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in Recommended Operating Conditions .
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101
±1000
UNIT
V
6.3 Recommended Operating Conditions
See
(1)
.
VCC Supply voltage
VIH
High-level input voltage
IO = –100 μA
VIL
Low-level input voltage
IO = 100 μA
VI
Input voltage
VO
Output voltage
IOH
High-level output current
MIN
MAX
1.65
5.5
0.75 × VCC
V
5.5
V
0
VCC
V
VCC = 1.65 V
–4
VCC = 2.3 V
–8
–16
VCC = 3 V
–32
4
8
16
VCC = 3 V
(1)
mA
24
VCC = 4.5 V
Operating free-air temperature
mA
–24
VCC = 2.3 V
TA
V
0
VCC = 1.65 V
Low-level output current
V
0.25 × VCC
VCC = 4.5 V
IOL
UNIT
32
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. For more information, see the
Implications of Slow or Floating CMOS Inputs application report.
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6.4 Thermal Information
SN74LVC1GU04
THERMAL METRIC
RθJA
(1)
Junction-to-ambient
thermal resistance
Junction-to-case
RθJC(top) (top) thermal
resistance
DBV
(SOT-23)
DCK
(SC70)
DRL
(SOT-5X3)
DRY
(SON)
DSF
(SON)
DPW
YZV
(X2SON) (DSBGA)
YZP
(DSBGA)
5 PINS
5 PINS
5 PINS
5 PINS
5 PINS
5 PINS
4 PINS
5 PINS
231.5
276.1
296.2
369.6
410.3
511
168.2
144.4
°C/W
139.4
178.9
137.3
257.6
208.4
241.9
2.1
1.3
°C/W
UNIT
RθJB
Junction-to-board
thermal resistance
71.1
70.9
145.3
230.8
262.6
374.2
55.9
39.9
°C/W
ψJT
Junction-to-top
characterization
parameter
45.2
47
14.7
77.2
36
45
1.1
0.5
°C/W
ψJB
Junction-to-board
characterization
parameter
70.7
69.3
145.9
231
262.3
373.3
56.3
39.7
°C/W
N/A
N/A
N/A
N/A
N/A
168.0
N/A
N/A
°C/W
Junction-to-case
RθJC(bot) (bottom) thermal
resistance
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range, TA = –40°C to +125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIL = 0 V, IOH = –100 µA, VCC = 1.65 V to 5.5 V
VOH
High-level output
voltage
MIN
TYP (1)
VIL = 0 V, IOH = –4 mA, VCC = 1.65 V
1.2
VIL = 0 V, IOH = –8 mA, VCC = 2.3 V
1.9
VIL = 0 V, IOH = –16 mA, VCC = 3 V
2.4
Low-level output
voltage
VIL = 0 V, IOH = –24 mA, VCC = 3 V
2.3
VIL = 0 V, IOH = –32 mA, VCC = 4.5 V
3.8
0.45
VIH = VCC, IOL = 8 mA, VCC = 2.3 V
0.3
VIH = VCC, IOL = 16 mA, VCC = 3 V
0.4
VIH = VCC, IOL = 24 mA, VCC = 3 V
0.55
VIH = VCC, IOL = 32 mA, VCC = 4.5 V
0.55
II
Input leakage current
ICC
Supply current
VI = 5.5 V or GND, IO = 0, VCC = 1.65 V to 5.5 V
CI
Input capacitance
VI = VCC or GND, VCC = 3.3 V, TA = –40°C to 85°C
(1)
6
0.1
VIH = VCC, IOL = 4 mA, VCC = 1.65 V
A Input:
VI = 5.5 V or GND, VCC = 0 V to 5.5 V
UNIT
V
VIH = VCC, IOL = 100 µA, VCC = 1.65 V to 5.5 V
VOL
MAX
VCC – 0.1
±5
10
7
V
μA
μA
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
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6.6 Switching Characteristics: TA = –40°C to +85°C
over recommended operating free-air temperature range (unless otherwise noted) (See Figure 2)
PARAMETER
tpd
TEST CONDITIONS
Propagation delay
A-to-Y
MIN
MAX
VCC = 1.8 V ± 0.15 V
1.3
5
VCC = 2.5 V ± 0.2 V
1
4
VCC = 3.3 V ± 0.3 V
1.1
3.7
1
3
MIN
MAX
VCC = 1.8 V ± 0.15 V
1.3
5.5
VCC = 2.5 V ± 0.2 V
1
4.5
VCC = 3.3 V ± 0.3 V
1.1
4.2
1
3.5
VCC = 5 V ± 0.5 V
UNIT
ns
6.7 Switching Characteristics: TA = –40°C to +125°C
over recommended operating free-air temperature range (unless otherwise noted) (See Figure 2)
PARAMETER
tpd
TEST CONDITIONS
Propagation delay
A-to-Y
VCC = 5 V ± 0.5 V
UNIT
ns
6.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
f = 10 MHz
TYP
VCC = 1.8 V
9
VCC = 2.5 V
11
VCC = 3.3 V
13
VCC = 5 V
27
UNIT
pF
6.9 Typical Characteristic
5
tpd(MAX)
4
3
tpd(ns)
2
tpd(MIN)
1
0
1
2
3
4
5
6
VCC (V)
Figure 1. tpd vs VCC
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
VM
VOL
tPHL
tPLZ
VLOAD/2
VM
tPZH
VM
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VOH
Output
VM
tPZL
tPHL
VM
Output
VI
Output
Control
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SN74LVC1GU04 device contains one inverter with an unbuffered output with a maximum sink current of
32 mA.
8.2 Functional Block Diagram
2
A
4
Y
Figure 3. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high-drive capability of this device
creates fast edges into light loads, so routing and load conditions must be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be
followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst-case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals that are applied to the inputs need to have fast edge rates, as shown by Δt/Δv in the Recommended
Operating Conditions, to avoid excessive current consumption and oscillations. If a slow or noisy input signal is
required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard
CMOS input.
8.3.3 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as shown in Figure 4.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
Device
VCC
Logic
Input
-IIK
Output
-IOK
GND
Figure 4. Electrical Placement of Clamping Diodes for Each Input and Output
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Feature Description (continued)
8.3.4 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics.
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
8.3.6 Unbuffered Logic
A standard CMOS logic function typically consists of at least three stages: the input inverter, the logic function,
and the output inverter. Some devices have multiple stages at the input or output for various reasons. An
unbuffered CMOS logic function eliminates the extra input and output stages; the device only contains the
required logic function which is directly driven from the inputs and directly drives the outputs.
The unbuffered inverter is commonly used in oscillator circuits because it is less sensitive to parameter changes
in the oscillator circuit due to having lower total gain than a buffered equivalent. To learn more about how to use
an unbuffered inverter in an oscillator circuit, see Use of the CMOS Unbuffered Inverter in Oscillator Circuits.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC1GU04.
Table 1. Function Table
10
INPUT
A
OUTPUT
Y
H
L
L
H
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The unbuffered inverter is commonly used in oscillator circuits because it is less sensitive to parameter changes
in the oscillator circuit due to having lower total gain than a buffered equivalent. An example application circuit is
shown in Figure 5. To learn more about how to use an unbuffered inverter in an oscillator circuit, refer to the Use
of the CMOS Unbuffered Inverter in Oscillator Circuits application report.
9.2 Typical Application
U
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Figure 5. Typical Application Diagram
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so
routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
To learn more about how to use an unbuffered inverter in an oscillator circuit, refer to the Use of the CMOS
Unbuffered Inverter in Oscillator Circuits application report.
1. Recommended Input Conditions
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in Recommended Operating
Conditions at any valid VCC.
2. Absolute Maximum Output Conditions
– Load currents must not exceed (IO max) per output and must not exceed (Continuous current through VCC
or GND) total current for the part. These limits are located in Absolute Maximum Ratings.
– Outputs must not be pulled above the voltage rated in the Absolute Maximum Ratings.
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Typical Application (continued)
9.2.3 Application Curve
1600
Icc
Icc
Icc
Icc
1400
1200
1.8V
2.5V
3.3V
5V
Icc - µA
1000
800
600
400
200
0
0
20
40
Frequency - MHz
60
80
D001
Figure 6. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
The VCC pin must have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is
recommended, and it is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-µF and 1µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power pin
as possible for best results.
12
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Product Folder Links: SN74LVC1GU04
SN74LVC1GU04
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SCES215Y – APRIL 1999 – REVISED DECEMBER 2017
11 Layout
11.1 Layout Guidelines
Even low data rate digital signals can contain high-frequency signal components due to fast edge rates. When a
printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs
primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414
times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance
and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore
some traces must turn corners. Figure 7 shows progressively better techniques of rounding corners. Only the last
example (BEST) maintains constant trace width and minimizes reflections.
An example layout is given in Figure 8 for the DPW (X2SON-5) package. This example layout includes a 0402
(metric) capacitor and uses the measurements found in the example board layout appended to this end of this
datasheet. A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be
used to trace out the center pin connection through another board layer, or it can be left out of the layout
11.2 Layout Example
WORST
BETTER
BEST
Figure 7. Trace Example
4 mil
0402
0.1 …F
Bypass
Capacitor
8 mil
8 mil
8 mil
SOLDER MASK
OPENING, TYP
METAL UNDER
SOLDER MASK,
TYP
Figure 8. Example Layout With DPW (X2SON-5) Package
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Product Folder Links: SN74LVC1GU04
13
SN74LVC1GU04
SCES215Y – APRIL 1999 – REVISED DECEMBER 2017
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
74LVC1GU04DBVRE4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CU4F
Samples
74LVC1GU04DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CU4F
Samples
74LVC1GU04DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CU4F
Samples
74LVC1GU04DCKRE4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CD5
CDS
Samples
74LVC1GU04DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CD5
CDS
Samples
74LVC1GU04DCKTG4
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CD5
CDS
Samples
74LVC1GU04DRLRG4
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CDR
Samples
SN74LVC1GU04DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CU45, CU4F, CU4J,
CU4R, CU4T)
(CU4H, CU4P, CU4S)
SN74LVC1GU04DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CU45, CU4F, CU4J,
CU4R)
(CU4H, CU4P, CU4S)
SN74LVC1GU04DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CD5, CDF, CDJ, CD
K, CDR, CDT)
(CDH, CDP, CDS)
SN74LVC1GU04DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CD5, CDF, CDJ, CD
K, CDR, CDT)
(CDH, CDP, CDS)
SN74LVC1GU04DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CM
Samples
SN74LVC1GU04DRLR
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CDR
Samples
SN74LVC1GU04DRY2
ACTIVE
SON
DRY
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CD
Samples
SN74LVC1GU04DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CD
Samples
Addendum-Page 1
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC1GU04DSFR
ACTIVE
SON
DSF
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CD
Samples
SN74LVC1GU04YZPR
ACTIVE
DSBGA
YZP
5
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
CDN
Samples
SN74LVC1GU04YZVR
ACTIVE
DSBGA
YZV
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
CD
(7, N)
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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