SN74LVC2244APWT

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN74LVC2244A SCAS572L – APRIL 1996 – REVISED JULY 2014 SN74LVC2244A Octal Buffer/Driver With 3-State Outputs 1 Features 2 Applications • • • • • • • • 1 • • • • • • Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 5.5 ns at 3.3 V Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Wearable Health and Fitness Devices Network Switches Servers Tests and Measurements 3 Description The SN74LVC2244A octal buffer/line driver designed for 1.65-V to 3.6-V VCC operation. is Device Information(1) PART NUMBER SN74LVC2244A PACKAGE BODY SIZE (NOM) SSOP (20) 7.20 mm × 5.30 mm SSOP (20) 8.65 mm × 3.90 mm TVSOP (20) 5.00 mm × 4.40 mm SOIC (20) 12.80 mm × 7.50 mm TSSOP (20) 6.50 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic 1OE 1A1 1A2 1A3 1A4 1 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC2244A SCAS572L – APRIL 1996 – REVISED JULY 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 4 4 5 5 6 6 6 7 7 Absolute Maximum Ratings ..................................... Handling Ratings....................................................... Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics, –40°C to 85°C................. Switching Characteristics, –40°C to 125°C............... Operating Characteristics.......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 8 9 Detailed Description .............................................. 9 9.1 9.2 9.3 9.4 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 9 9 9 9 10 Application and Implementation........................ 10 10.1 Application Information.......................................... 10 10.2 Typical Application ............................................... 10 11 Power Supply Recommendations ..................... 11 12 Layout................................................................... 11 12.1 Layout Guidelines ................................................. 11 12.2 Layout Example .................................................... 11 13 Device and Documentation Support ................. 12 13.1 Trademarks ........................................................... 12 13.2 Electrostatic Discharge Caution ............................ 12 13.3 Glossary ................................................................ 12 14 Mechanical, Packaging, and Orderable Information ........................................................... 12 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision K (March 2005) to Revision L Page • Updated document to new TI data sheet standards. ............................................................................................................. 1 • Deleted Ordering Information table. ....................................................................................................................................... 1 • Changed Ioff bullet in Features list. ......................................................................................................................................... 1 • Added Applications. ................................................................................................................................................................ 1 • Added Pin Functions table...................................................................................................................................................... 3 • Added Handling Ratings table. ............................................................................................................................................... 4 • Changed MAX ambient temperature to 125°C in Recommended Operating Conditions. .................................................... 5 • Added Thermal Information table. .......................................................................................................................................... 5 • Added –40°C to 125°C temperature range in Electrical Characteristics table. ...................................................................... 6 • Added data to Switching Characteristics, –40°C to 85°C....................................................................................................... 6 • Added Switching Characteristics table, –40°C to 125°C. ...................................................................................................... 6 • Changed Operating Characteristics table............................................................................................................................... 7 • Added Typical Characteristics. ............................................................................................................................................... 7 • Added Detailed Description section........................................................................................................................................ 9 • Added Application and Implementation section.................................................................................................................... 10 2 Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC2244A SN74LVC2244A www.ti.com SCAS572L – APRIL 1996 – REVISED JULY 2014 6 Pin Configuration and Functions DB, DBQ, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 20 2 3 19 18 4 5 17 16 6 7 15 14 8 9 13 12 10 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 Pin Functions PIN NO. NAME I/O DESCRIPTION 1 1OE I Output Enable 1 2 1A1 I 1A1 Input 3 2Y4 O 2Y4 Output 4 1A2 I 1A2 Input 5 2Y3 O 2Y3 Output 6 1A3 I 1A3 Input 7 2Y2 O 2Y2 Output 8 1A4 I 1A4 Input 9 2Y1 O 2Y1 Output 10 GND — Ground Pin 11 2A1 I 2A1 Input 12 1Y4 O 1Y4 Output 13 2A2 I 2A2 Input 14 1Y3 O 1Y3 Output 15 2A3 I 2A3 Input 16 1Y2 O 1Y2 Output 17 2A4 I 2A4 Input 18 1Y1 O 1Y1 Output 19 2OE I Output Enable 2 20 VCC — Power Pin Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC2244A 3 SN74LVC2244A SCAS572L – APRIL 1996 – REVISED JULY 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX Supply voltage range –0.5 6.5 UNIT V (2) VI Input voltage range –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA (3) Continuous current through VCC or GND (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the Recommended Operating Conditions table. 7.2 Handling Ratings Tstg V(ESD) (1) (2) 4 MIN MAX UNIT –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 0 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 0 1000 Storage temperature range Electrostatic discharge V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC2244A SN74LVC2244A www.ti.com SCAS572L – APRIL 1996 – REVISED JULY 2014 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage VIH High-level input voltage Operating Data retention only MIN MAX 1.65 3.6 1.5 VCC = 1.65 V to 1.95 V Low-level input voltage VI Input voltage 1.7 VCC = 2.7 V to 3.6 V 2 V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V VO Output voltage IOH High-level output current Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 1.65 V –2 VCC = 2.3 V –4 VCC = 2.7 V –8 V V mA –12 VCC = 1.65 V 2 VCC = 2.3 V 4 VCC = 2.7 V 8 VCC = 3 V (1) V 0.8 0 VCC = 3 V IOL V 0.65 × VCC VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V VIL UNIT mA 12 –40 10 ns/V 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). 7.4 Thermal Information SN74LVC2244A THERMAL METRIC (1) DB DBQ DGV DW NS PW UNIT 20 PINS RθJA Junction-to-ambient thermal resistance 94.5 94.7 114.7 88.3 74.7 102.5 RθJC(top) Junction-to-case (top) thermal resistance 56.2 47.9 29.8 51.1 40.5 35.9 RθJB Junction-to-board thermal resistance 49.7 45.0 56.2 50.9 42.3 53.5 ψJT Junction-to-top characterization parameter 18.1 11.0 0.8 20.0 14.3 2.2 ψJB Junction-to-board characterization parameter 49.5 44.6 55.5 50.5 41.9 52.9 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a n/a n/a (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC2244A 5 SN74LVC2244A SCAS572L – APRIL 1996 – REVISED JULY 2014 www.ti.com 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS –40°C to 125°C MIN TYP (1) MAX MAX VCC – 0.2 1.65 V 1.2 1.2 2.3 V 1.7 1.7 2.7 V 2.2 2.2 IOH = –6 mA 3V 2.4 2.4 IOH = –8 mA 2.7 V 2 2 IOH = –12 mA 3V 2 2 IOL = 100 μA 1.65 V to 3.6 V 0.2 0.2 1.65 V 0.45 0.45 2.3 V 0.7 0.7 2.7 V 0.4 0.4 IOL = 6 mA 3V 0.55 0.55 IOL = 8 mA 2.7 V 0.6 0.6 IOL = 12 mA 3V 0.8 0.8 IOH = –4 mA IOL = 2 mA IOL = 4 mA UNIT V V 3.6 V ±5 ±5 μA Ioff VI or VO = 5.5 V 0 ±10 ±10 μA IOZ VO = 0 to 5.5 V 3.6 V ±10 ±10 μA 10 10 10 10 500 500 II ICC ΔICC (1) (2) TYP (1) VCC – 0.2 IOH = –2 mA VOL MIN 1.65 V to 3.6 V IOH = –100 μA VOH –40°C to 85°C VCC VI = 0 to 5.5 V VI = VCC or GND 3.6 V ≤ VI ≤ 5.5 V (2) IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND 3.6 V 2.7 V to 3.6 V μA μA Ci VI = VCC or GND 3.3 V 4 4 pF Co VO = VCC or GND 3.3 V 5.5 5.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. This applies in the disabled state only. 7.6 Switching Characteristics, –40°C to 85°C over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) VCC = 1.8 V ± 0.15 V FROM (INPUT) TO (OUTPUT) tpd A Y 10.9 ten OE Y 12.6 tdis OE Y 12.1 PARAMETER MIN MAX VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX 7.9 6.4 1.5 5.5 ns 9.6 8.1 1 7.1 ns 7.8 7.3 1.5 6.8 ns 7.7 Switching Characteristics, –40°C to 125°C over operating free-air temperature range (unless otherwise noted) 6 VCC = 1.8 V ± 0.15 V FROM (INPUT) TO (OUTPUT) tpd A Y 12.4 ten OE Y tdis OE Y PARAMETER MIN MAX VCC = 2.5 V ± 0.2 V MIN MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX 10 7.1 1.5 6.5 ns 14.1 11.7 8.5 1 7.8 ns 13.6 9.9 7.8 1.5 7.6 ns Submit Documentation Feedback MAX VCC = 2.7 V Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC2244A SN74LVC2244A www.ti.com SCAS572L – APRIL 1996 – REVISED JULY 2014 7.8 Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Power dissipation capacitance per buffer/driver Cpd Outputs enabled VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP 43 43 46 1 1 2 f = 10 MHz Outputs disabled UNIT pF 7.9 Typical Characteristics 4 6 TDP in ns 3.5 5 4 2.5 TDP (ns) TPD (ns) 3 2 1.5 3 2 1 1 0.5 TPD in ns 0 -100 0 -50 0 50 Temperature (qC) 100 150 0 0.5 D001 Figure 1. SN74LVC2244A TPD Across Temperature at 3.3 V 1 1.5 2 VCC (V) 2.5 3 3.5 D002 Figure 2. SN74LVC2244A TDP Across VCC at 25°C Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC2244A 7 SN74LVC2244A SCAS572L – APRIL 1996 – REVISED JULY 2014 www.ti.com 8 Parameter Measurement Information VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V VOH VM Output VM VOL VM tPLZ VLOAD/2 VM tPZH VOH Output VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC2244A SN74LVC2244A www.ti.com SCAS572L – APRIL 1996 – REVISED JULY 2014 9 Detailed Description 9.1 Overview This octal buffer and line driver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC2244A device is organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. The outputs, which are designed to sink up to 12 mA, include equivalent 26-ohm resistors to reduce overshoot and undershoot. 9.2 Functional Block Diagram 1OE 1A1 1A2 1A3 1A4 1 19 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 9.3 Feature Description • • • Wide operating voltage range – Operates from 1.65 V to 3.6 V Allows down voltage translation – Inputs accept voltages to 5.5 V Ioff Feature – Allows voltages on the inputs and outputs when VCC is 0 V 9.4 Device Functional Modes Table 1. Function Table (Each Buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC2244A 9 SN74LVC2244A SCAS572L – APRIL 1996 – REVISED JULY 2014 www.ti.com 10 Application and Implementation 10.1 Application Information Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 10.2 Typical Application Regulated 3.3 V OE A1 VCC Y1 µC System Logic µC or A4 LEDs Y4 System Logic GND Figure 4. Typical Application Diagram 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. 10.2.2 Detailed Design Procedure 1. Recommended Input Conditions – Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table. – Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC. 2. Recommend Output Conditions – Load currents should not exceed 25 mA per output and 50 mA total for the part. – Outputs should not be pulled above VCC. 10 Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC2244A SN74LVC2244A www.ti.com SCAS572L – APRIL 1996 – REVISED JULY 2014 Typical Application (continued) 10.2.3 Application Curves 300 250 ICC (mA) 200 150 100 ICC 1.8 V ICC 2.5 V ICC 3.3 V 50 0 0 10 20 30 40 Frequency (MHz) 50 60 D003 Figure 5. ICC vs Frequency 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a 1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 12 Layout 12.1 Layout Guidelines When using multiple-bit logic devices, inputs should never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the part when asserted. This will not disable the input section of the IOs, so they cannot float when disabled. 12.2 Layout Example Vcc Unused Input Input Output Unused Input Output Input Figure 6. Layout Diagram Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC2244A 11 SN74LVC2244A SCAS572L – APRIL 1996 – REVISED JULY 2014 www.ti.com 13 Device and Documentation Support 13.1 Trademarks All trademarks are the property of their respective owners. 13.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC2244A PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LVC2244ADBQR ACTIVE SSOP DBQ 20 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVC2244A Samples SN74LVC2244ADBQRE4 ACTIVE SSOP DBQ 20 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVC2244A Samples SN74LVC2244ADBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A Samples SN74LVC2244ADBRG4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A Samples SN74LVC2244ADGVR ACTIVE TVSOP DGV 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A Samples SN74LVC2244ADW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A Samples SN74LVC2244ADWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A Samples SN74LVC2244ADWRE4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A Samples SN74LVC2244ANSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A Samples SN74LVC2244APW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A Samples SN74LVC2244APWG4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A Samples SN74LVC2244APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A Samples SN74LVC2244APWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A Samples SN74LVC2244APWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A Samples SN74LVC2244APWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of