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SN54LVC257A, SN74LVC257A
SCAS294O – JANUARY 1993 – REVISED JUNE 2015
SNx4LVC257A Quadruple 2-Line to 1-Line Data Selectors and
Multiplexers With 3-State Outputs
1 Features
3 Description
•
•
•
•
These quadruple 2-line to 1-line data selectors and
multiplexers are designed for 1.65-V to 3.6-V VCC
operation.
1
•
•
•
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Maximum tpd of 4.6 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
2 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
On Products Compliant to MIL-PRF-38535, All
Parameters Are Tested Unless Otherwise Noted.
On All Other Products, Production Processing
Does Not Necessarily Include Testing of All
Parameters.
The SNx4LVC257A devices are designed to multiplex
signals from 4-bit data sources to 4-output data lines
in bus-organized systems. The 3-state outputs do not
load the data lines when the output-enable (OE) input
is at a high logic level.
Inputs can be driven from either 3.3-V or 5-V devices.
This feature allows the use of these devices as
translators in a mixed 3.3-V or 5-V system
environment.
Device Information(1)
PART NUMBER
PACKAGE
SN74LVC257A
2 Applications
•
•
•
•
•
•
•
Cable Modem Termination Systems
Tests and Measurements
I/O Expanders
Motor Drivers
Network Switches
Servers
Telecom Infrastructure
SN54LVC257A
BODY SIZE (NOM)
VQFN (16)
3.50 mm × 4.00 mm
SOIC (16)
9.90 mm × 3.91 mm
SO (16)
10.30 mm × 5.30 mm
SSOP (16)
5.50 mm × 6.20 mm
TSSOP (16)
4.40 mm × 5.00 mm
CDIP (16)
6.92 mm × 21.34 mm
CFP (16)
10.30 mm × 6.73 mm
LCCC (20)
8.89 mm × 8.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
OE
A/B
1A
15
1
2
4
1B
2A
1Y
3
5
7
2Y
6
2B
3A
11
9
3B
4A
4B
3Y
10
14
12
4Y
13
Pin numbers shown are for the D, DB, J, NS, PW , RGY , and W packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LVC257A, SN74LVC257A
SCAS294O – JANUARY 1993 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
5
5
6
6
6
7
7
7
8
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information: 16-Pin Packages.....................
Thermal Information: 20-Pin Package ......................
Electrical Characteristics...........................................
SN54LVC257A Switching Characteristics ................
SN74LVC257A Switching Characteristics ................
Operating Characteristics..........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ............................................... 11
11 Power Supply Recommendations ..................... 13
12 Layout................................................................... 13
12.1 Layout Guidelines ................................................. 13
12.2 Layout Example .................................................... 13
13 Device and Documentation Support ................. 14
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
14
14 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (June 2005) to Revision O
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SCAS294O – JANUARY 1993 – REVISED JUNE 2015
5 Device Options
PART NUMBER
SN74LVC257ARGYR
PACKAGE
BODY SIZE
VQFN
3.50 mm × 4.00 mm
SOIC
3.90 mm × 9.90 mm
SN74LVC257ANSR
SO
5.30 mm × 10.10 mm
SN74LVC257ADBR
SSOP
5.50 mm × 6.20 mm
TSSOP
4.40 mm × 5.00 mm
SNJ54LVC257AJ
CDIP
6.92 mm × 21.34 mm
SNJ54LVC257AW
CFP
13.70 mm × 10.10 mm
SNJ54LVC257AFK
LCCC
8.89 mm × 8.89 mm
SN74LVC257AD
SN74LVC257ADT
SN74LVC257APW
SN74LVC257APWT
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6 Pin Configuration and Functions
D, DB, NS, J, W, or PW Package
16-Pin SOIC, SSOP, SO, CDIP, CFP, or TSSOP
Top View
3
14
4
13
5
12
6
11
7
10
8
9
VCC
OE
4A
4B
4Y
3A
3B
3Y
1A
1B
1Y
2A
2B
2Y
VCC
15
1
16
2
15 OE
3
14 4A
4
13 4B
5
12 4Y
6
11
7
10 3B
8
9
3Y
16
2
A/B
1
GND
A/B
1A
1B
1Y
2A
2B
2Y
GND
RGY Package
16-Pin VQFN with Exposed Thermal Pad
Top View
3A
1A
A/B
NC
VCC
OE
FK Package
20-Pin LCCC
Top View
4
3
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
4B
NC
4Y
3A
2Y
GND
NC
3Y
3B
1B
1Y
NC
2A
2B
Pin Functions
PIN
SOIC, SSOP, SO,
CDIP, CFP,
TSSOP, or VQFN
LCCC
A/B
1
2
I
1A
2
3
I/O
Multiplexer Signal Input
1B
3
4
I/O
Multiplexer Signal Input
1Y
4
5
I/O
Multiplexer Output
2A
5
7
I/O
Multiplexer Signal Input
2B
6
8
I/O
Multiplexer Signal Input
2Y
7
9
I/O
Multiplexer Output
3A
11
14
I/O
Multiplexer Signal Input
3B
10
13
I/O
Multiplexer Signal Input
3Y
9
12
I/O
Multiplexer Output
4A
14
18
I/O
Multiplexer Signal Input
4B
13
17
I/O
Multiplexer Signal Input
4Y
12
15
I/O
Multiplexer Output
GND
8
10
—
Ground
NC (1)
—
1, 6, 11, 16
—
No connect
OE
15
19
I/O
Active low Output enable
VCC
16
20
—
Power pin
NAME
(1)
4
I/O
DESCRIPTION
Select Pin, Low selects A, High selects B
NC – no internal connection
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
(2)
MIN
MAX
UNIT
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
V
VI
Input voltage
VO
Output voltage (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
150
°C
Tstg
(1)
(2)
(3)
(3)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
See
(1)
SN54LVC257A
VCC
MIN
MAX
MIN
MAX
2
3.6
1.65
3.6
Operating
Supply voltage
SN74LVC257A
Data retention only
1.5
High-level input voltage
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
Low-level input voltage
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VI
Input voltage
VO
Output voltage
V
2
VCC = 1.65 V to 1.95 V
VIL
0.8
0
5.5
0
5.5
V
0
VCC
0
VCC
V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
–4
VCC = 2.3 V
High-level output current
V
0.8
VCC = 1.65 V
IOH
V
1.5
VCC = 1.65 V to 1.95 V
VIH
UNIT
–8
VCC = 2.7 V
–12
–12
VCC = 3 V
–24
–24
VCC = 1.65 V
4
VCC = 2.3 V
8
mA
mA
VCC = 2.7 V
12
12
VCC = 3 V
24
24
10
10
ns/V
85
°C
–55
125
–40
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
7.4 Thermal Information: 16-Pin Packages
SN54LVC257A, SN74LVC257A
THERMAL METRIC (1)
D (SOIC) (2)
DB (SSOP) (2)
NS (SO) (2)
PW (TSSOP) (2)
UNIT
64
108
°C/W
16 PINS
RθJA
(1)
(2)
Junction-to-ambient thermal resistance
73
82
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
7.5 Thermal Information: 20-Pin Package
SN54LVC257A
THERMAL METRIC (1)
RGY (LCCC) (2)
UNIT
20 PINS
RθJA
(1)
(2)
6
Junction-to-ambient thermal resistance
39
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-5.
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7.6 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
MIN TYP
IOH = –100 μA
1.65 V to 3.6 V
IOH = –100 μA
2.7 V to 3.6 V
IOH = –4 mA
1.65 V
IOH = –8 mA
2.3 V
IOH = –12 mA
IOH = –24 mA
(1)
SN74LVC257A
MIN TYP (1)
MAX
MAX
UNIT
VCC – 0.2
VCC – 0.2
1.2
1.7
2.7 V
2.2
2.2
3V
2.4
2.4
3V
2.2
2.2
V
1.65 V to 3.6 V
IOL = 100 μA
VOL
SN54LVC257A
VCC
0.2
2.7 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
0.4
IOL = 24 mA
3V
0.55
0.55
V
II
VI = 5.5 V or GND
3.6 V
±5
±5
μA
IOZ
VO = VCC or GND
3.6 V
±15
±10
μA
ICC
VI = VCC or GND,
3.6 V
10
10
μA
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.7 V to 3.6 V
500
500
μA
Ci
VI = VCC or GND
3.3 V
5
5
pF
Co
VO = VCC or GND
3.3 V
5
5
pF
(1)
IO = 0
All typical values are at VCC = 3.3 V, TA = 25°C.
7.7 SN54LVC257A Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN54LVC257A
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 2.7 V
MIN
A or B
tpd
Y
A/B
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
5.4
1
4.6
7.5
1
6.4
ns
ten
OE
Y
6.7
1
5.6
ns
tdis
OE
Y
4.7
0.5
4.3
ns
1
ns
tsk(o)
7.8 SN74LVC257A Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN74LVC257A
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
A/B
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
13.5
1
7.4
1
5.4
1
4.6
1
15.6
1
9.5
1
7.5
1
6.4
ns
ten
OE
Y
1
14.6
1
8.7
1
6.7
1
5.6
ns
tdis
OE
Y
1
15.4
1
6.7
1
4.7
1
4.3
ns
1
ns
tsk(o)
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7.9 Operating Characteristics
TA = 25°C
Cpd
PARAMETER
TEST CONDITIONS
Power dissipation capacitance
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
13.5
14.5
15.5
UNIT
pF
7.10 Typical Characteristics
10
14
12
VCC = 3 V,
TA = 25°C
tpd – Propagation Delay Time – ns
tpd – Propagation Delay Time – ns
VCC = 3 V,
TA = 25°C
One Output Switching
Four Outputs Switching
Eight Outputs Switching
10
8
6
4
6
4
2
2
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 1. Propagation Delay (Low to High Transition)
vs Load Capacitance
8
One Output Switching
Four Outputs Switching
Eight Outputs Switching
8
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0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 2. Propagation Delay (High to Low Transition)
vs Load Capacitance
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V±0.15 V
2.5 V±0.2 V
2.7 V
3.3 V±0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
VΔ
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500Ω
500Ω
500Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + VΔ
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH − VΔ
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z O = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
These quadruple 2-line to 1-line data selectors and multiplexers are designed for 1.65-V to 3.6-V VCC operation.
The SNx4LVC257A devices are designed to multiplex signals from 4-bit data sources to 4-output data lines in
bus-organized systems. The 3-state outputs do not load the data lines when the output-enable (OE) input is at a
high logic level.
9.2 Functional Block Diagram
OE
A/B
1A
15
1
2
4
1B
2A
1Y
3
5
7
2Y
6
2B
3A
11
9
3B
4A
4B
3Y
10
14
12
4Y
13
9.3 Feature Description
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V and 5-V system environment. Device features a maximum tpd of 4.6 ns allowing the device to be
used in high-speed applications as well.
To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
9.4 Device Functional Modes
Table 1 lists the functional modes for the SN54LVC257A and SN74LVC257A devices.
Table 1. Function Table
INPUTS
10
OE
A/B
A
B
OUTPUT
Y
H
X
X
X
Z
L
L
L
X
L
L
L
H
X
H
L
H
X
L
L
L
H
X
H
H
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SNx4LVC257A devices are useful for digital signal data selector or multiplexer applications.
10.2 Typical Application
The SNx4LVC257A devices use CMOS technology and have balanced output drive. These devices can be used
for down level translation and multiplexer function as shown in Figure 4.
Vcc=1.65V to 3.6V
Vcc=1.65V to 5V
0.1uF
Vcc
A/B
1A
Vcc=1.65V to 3.6V
Cbypass
Gnd
1Y
1B
Processor 1
Digital Signals
2A
Or
2B
2Y
Processor 2
Digital Sensor Array
3A
3Y
3B
4A
4Y
4B
OE
When 0, Y is high impedance
Figure 4. SNx4LVC257A Used as Level Translation and as a Multiplexer
10.2.1 Design Requirements
Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high
drive will also create fast edges into light loads so routing and load conditions must be considered to prevent
ringing.
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11
SN54LVC257A, SN74LVC257A
SCAS294O – JANUARY 1993 – REVISED JUNE 2015
www.ti.com
Typical Application (continued)
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specification, see (Δt/ΔV) in the Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are over voltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions
– Load currents must not exceed (IO max) per output and must not exceed (continuous current through VCC
or GND) total current for the part. These limits are in the Recommended Operating Conditions table.
– Outputs must not be pulled above VCC.
10.2.3 Application Curves
60
100
80
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
40
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
20
I OH – mA
I OL – mA
60
40
0
–20
–40
20
–60
0
–80
–20
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VOL – V
Figure 5. Output Drive Current (IOL)
vs LOW-level Output Voltage (VOL)
12
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1.4
1.6
–100
–1
–0.5 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOH – V
Figure 6. Output Drive Current (IOH)
vs HIGH-level Output Voltage (VOH)
Copyright © 1993–2015, Texas Instruments Incorporated
Product Folder Links: SN54LVC257A SN74LVC257A
SN54LVC257A, SN74LVC257A
www.ti.com
SCAS294O – JANUARY 1993 – REVISED JUNE 2015
11 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. If there are multiple VCC terminals then 0.01-μF or 0.022-μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor must be installed as close to the power terminal as possible for the best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
12.2 Layout Example
VCC
Input
Unused Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagrams
Copyright © 1993–2015, Texas Instruments Incorporated
Product Folder Links: SN54LVC257A SN74LVC257A
Submit Documentation Feedback
13
SN54LVC257A, SN74LVC257A
SCAS294O – JANUARY 1993 – REVISED JUNE 2015
www.ti.com
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LVC257A
Click here
Click here
Click here
Click here
Click here
SN74LVC257A
Click here
Click here
Click here
Click here
Click here
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
14
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Copyright © 1993–2015, Texas Instruments Incorporated
Product Folder Links: SN54LVC257A SN74LVC257A
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-0050901QFA
ACTIVE
CFP
W
16
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-0050901QF
A
SNJ54LVC257AW
SN74LVC257AD
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC257A
SN74LVC257ADBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LC257A
SN74LVC257ADBRG4
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LC257A
SN74LVC257ADR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC257A
SN74LVC257ADRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC257A
SN74LVC257ANSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC257A
SN74LVC257APW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LC257A
SN74LVC257APWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
LC257A
SN74LVC257APWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LC257A
SN74LVC257APWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LC257A
SN74LVC257ARGYR
ACTIVE
VQFN
RGY
16
3000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LC257A
SNJ54LVC257AW
ACTIVE
CFP
W
16
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-0050901QF
A
SNJ54LVC257AW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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