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SN74LVC2G00
SCES193N – APRIL 1999 – REVISED JANUARY 2015
SN74LVC2G00 Dual 2-Input Positive-NAND Gate
1 Features
3 Description
•
This dual 2-input positive-NAND gate is designed for
1.65-V to 5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4.3 ns at 3.3 V
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Live Insertion, Partial Power
Down Mode, and Back Drive Protection
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 1000-V Charged-Device Model
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IP Phones: Wired and Wireless
Optical Modules
Optical Networking: EPON and Video Over Fiber
Point-to-Point Microwave Backhaul
Power: Telecom DC/DC Module:
Analog and Digital
Private Branch Exchanges (PBX)
TETRA Base Exchanges
Telecom Base Band Units
Telecom Shelters: Power Distribution Units (PDU),
Power Monitoring Units (PMU), Wireless Battery
Monitoring, Remote Electrical Tilt Units (RET),
Remote Radio Units (RRU), Tower Mounted
Amplifiers (TMA)
Vector Signal Analyzers and Generators
Video Conferencing: IP-Based HD
WiMAX and Wireless Infrastructure Equipment
Wireless Communications Testers and
Wireless Repeaters
xDSL Modems and DSLAM
The SN74LVC2G00 device performs the Boolean
function Y = A × B or Y = A + B in positive logic.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
SN74LVC2G00
PACKAGE
BODY SIZE (NOM)
SM8 (8)
2.95 mm × 2.80 mm
US8 (8)
2.30 mm × 2.00 mm
DSBGA (8)
1.91 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
1
7
1A
1Y
2
1B
5
3
2A
6
2Y
2B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2G00
SCES193N – APRIL 1999 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
4
4
5
5
6
6
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Electrical Characteristics (Continued).......................
Switching Characteristics, -40°C to 85°C ................
Switching Characteristics, -40°C to 125°C ..............
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
9
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 12
13.1 Trademarks ........................................................... 12
13.2 Electrostatic Discharge Caution ............................ 12
13.3 Glossary ................................................................ 12
14 Mechanical, Packaging, and Orderable
Information ........................................................... 12
5 Revision History
Changes from Revision M (November 2013) to Revision N
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
Changes from Revision L (January 2007) to Revision M
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Updated operating temperature range in Recommended Operating Conditions table. ......................................................... 5
•
Added ESD warning. ............................................................................................................................................................ 12
2
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6 Pin Configuration and Functions
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
1A
1
8
VCC
1B
2
7
1Y
2Y
3
6
2B
GND
4
5
2A
1A
1B
2Y
GND
8
1
2
7
3
6
4
5
YZP PACKAGE
(BOTTOM VIEW)
VCC
1Y
2B
2A
GND
2Y
1B
1A
4 5
3 6
2 7
1 8
2A
2B
1Y
VCC
See mechanical drawings for dimensions.
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
DCT, DCU, YZP
1A
1
I
A input for gate 1
1B
2
I
B input for gate 1
2Y
3
O
Output for gate 2
GND
4
—
Ground
2A
5
I
A input for gate 2
2B
6
I
B input for gate 2
1Y
7
O
Output for gate 1
VCC
8
I
Power input.
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SCES193N – APRIL 1999 – REVISED JANUARY 2015
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature range
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
VCC
Operating
Supply voltage
Data retention only
High-level input voltage
MAX
5.5
1.7
VCC = 3 V to 3.6 V
VI
Input voltage
VO
Output voltage
0.7 × VCC
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
IOH
High-level output current
V
2
VCC = 1.65 V to 1.95 V
Low-level input voltage
0.3 × VCC
5.5
V
0
VCC
V
VCC = 1.65 V
–4
VCC = 2.3 V
–8
–16
VCC = 3 V
–32
4
VCC = 2.3 V
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
8
16
VCC = 3 V
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
(1)
mA
–24
VCC = 1.65 V
Low-level output current
V
0
VCC = 4.5 V
IOL
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 4.5 V to 5.5 V
VIL
UNIT
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
1.65
ns/V
5
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
SN74LVC1G00
THERMAL METRIC (1)
RθJA
(1)
Junction-to-ambient thermal resistance
DCT
DCU
YZP
5 PINS
5 PINS
5 PINS
220
227
102
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
VOH
1.65 V to 5.5 V
MIN
VCC – 0.1
1.2
1.2
IOH = –8 mA
2.3 V
1.9
1.9
2.4
2.4
2.3
2.3
3V
3.8
TYP (1)
MAX
4.5 V
IOL = 100 μA
1.65 V to 5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
3.8
0.4
0.4
0.55
0.55
0.55
0.55
3V
IOL = 32 mA
4.5 V
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
CI
VI = VCC or GND
IO = 0
UNIT
V
IOH = –32 mA
IOL = 24 mA
(1)
MAX
VCC – 0.1
IOL = 16 mA
A or B inputs
–40°C to 125°C
TYP (1)
1.65 V
IOH = –24 mA
II
MIN
IOH = –4 mA
IOH = –16 mA
VOL
–40°C to 85°C
VCC
V
0 to 5.5 V
±5
±5
μA
0
±10
±10
μA
1.65 V to 5.5 V
10
10
μA
3 V to 5.5 V
500
500
μA
3.3 V
5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
7.6 Electrical Characteristics (Continued)
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
19
19
20
22
f = 10 MHz
UNIT
pF
7.7 Switching Characteristics, -40°C to 85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.7
8.6
1.6
4.8
1.1
4.3
1
3.3
ns
7.8 Switching Characteristics, -40°C to 125°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to 125°C
6
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.7
9.4
1.6
5.5
1.1
4.9
1
3.8
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ns
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7.9 Typical Characteristics
8
6
TPD
7
5
6
TPD - ns
TPD - ns
4
3
5
4
3
2
2
1
1
TPD
0
-100
0
-50
0
50
Temperature - °C
100
150
0
1
D001
Figure 1. TPD vs Temperature at 3.3-V VCC
2
3
Vcc - V
4
5
Product Folder Links: SN74LVC2G00
D002
Figure 2. TPD vs VCC at 25°C
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7
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
The SN74LVC2G00 device contains two 2-input positive-NAND gates and performs the Boolean function
Y = A × B or Y = A + B on each gate. This device is fully specified for partial-power-down applications using Ioff.
The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is
powered down.
9.2 Functional Block Diagram
1
7
1A
1Y
2
1B
5
3
2A
2Y
6
2B
9.3 Feature Description
•
•
•
Wide operating voltage range.
– Operates from 1.65 V to 5.5 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff feature
– Allows voltages on the inputs and outputs, when VCC is 0 V
9.4 Device Functional Modes
Table 1. Function Table (Each Gate)
INPUTS
A
B
OUTPUT
Y
H
H
L
L
X
H
X
L
H
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10 Application and Implementation
10.1 Application Information
SN74LVC2G00 is a high-drive CMOS device that can be used for implementing NAND logic with a high output
drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V, making it Ideal for driving
multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5-V tolerant, allowing it to
translate down to VCC.
10.2 Typical Application
1.65 V to 5.5 V
1
8
2
7
3
6
From microcontroller / logic
From microcontroller / logic
4
5
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specifications, see (Δt/ΔV) in the Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed total current (continuous
current through VCC or GND) for the part. These limits are located in the Absolute Maximum Ratings
table.
– Outputs should not be pulled above VCC.
10
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Typical Application (continued)
10.2.3 Application Curves
10
8
VCC
VCC
VCC
VCC
1.8 V
2.5 V
3.3 V
5V
ICC - mA
6
4
2
0
-2
-20
0
20
40
Frequency - MHz
60
80
D003
Figure 4. ICC vs Frequency (Each Gate)
11 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
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12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 5 are the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient.
12.2 Layout Example
Vcc
Input
Unused Input
Output
Unused Input
Output
Input
Figure 5. Layout Diagram
13 Device and Documentation Support
13.1 Trademarks
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVC2G00DCT3
ACTIVE
SM8
DCT
8
3000
RoHS &
Non-Green
SNBI
Level-1-260C-UNLIM
-40 to 125
C00
Z
SN74LVC2G00DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C00
(R, Z)
SN74LVC2G00DCTRE4
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C00
(R, Z)
SN74LVC2G00DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C00J, C00Q, C00R)
SN74LVC2G00DCUT
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C00J, C00Q, C00R)
SN74LVC2G00DCUTG4
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C00R
SN74LVC2G00YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
CAN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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